Integrated circuit package substrate

Patent metadata

Field	Value
Publication number	US-2018098436-A1
Application number	US-201715821532-A
Country	US
Kind code	A1
Filing date	Nov 22, 2017
Priority date	Apr 25, 2013
Publication date	Apr 5, 2018
Grant date	—

Abstract

Embodiments of the present disclosure are directed towards techniques and configurations for dual surface finish package substrate assemblies. In one embodiment a method includes depositing a first surface finish on one or more electrical routing features located on a first side of a package substrate and on one or more lands located on a second side of the package substrate, the second side being opposite the first side of the substrate. The method may further include removing the first surface finish on the first side of the package substrate; and depositing a second surface finish on the one or more electrical routing features of the first side. The depositing of the second surface finish may be accomplished by one of a Direct Immersion Gold (DIG) process or an Organic Solderability Preservative (OSP) process. Other embodiments may be described and/or claimed.

First claim

What is claimed is:

1 . A method of forming an integrated circuit (IC) package substrate comprising:
depositing a first surface finish on one or more electrical routing features disposed on a first side of a package substrate and on one or more lands disposed on a second side of the package substrate, the second side being disposed opposite to the first side; removing the first surface finish on the first side of the package substrate; and depositing a second surface finish on the one or more electrical routing features, wherein the depositing of the second surface finish is accomplished by one of a Direct Immersion Gold (DIG) process or an Organic Solderability Preservative (OSP) process.

2 . The method of claim 1 , wherein the depositing of the second surface finish is accomplished by a Direct Immersion Gold (DIG) process.

3 . The method of claim 1 , wherein the depositing of the second surface finish is accomplished by an Organic Solderability Preservative (OSP) process.

4 . The method of claim 1 , wherein the depositing of the first surface finish on one or more die bond pads and one or more lands occurs simultaneously using a plating process.

5 . The method of claim 1 , wherein a planarizing process is used, at least in part, in removing the first surface finish on the first side.

6 . The method of claim 1 , further comprising forming the electrical routing features using a method comprising:
laminating a dielectric material over a metal conductor to form a dielectric layer; selectively removing, by a laser, dielectric material to form voids in the dielectric layer revealing the metal conductor; plating a fill metal into the voids created by the laser; and planarizing the fill metal to a level even with a surface of the dielectric layer.

7 . The method of claim 1 , wherein depositing the first surface finish is performed using an electroless plating process.

8 . The method of claim 1 , wherein depositing the first surface finish comprises depositing nickel (Ni).

9 . The method of claim 8 , wherein depositing the first surface finish further comprises depositing one or both of palladium or gold.

10 . The method of claim 9 , wherein depositing the first surface finish comprises depositing gold using an electroless nickel-immersion gold (ENIG+EG) process.

11 . A package assembly comprising:
an integrated circuit (IC) chip having one or more input/output (I/O) connection points and one or more power connection points; and a package substrate including:
a first side including one or more lands, the one or more lands having a first surface finish disposed on the one or more lands; and
a second side disposed opposite to the first side, the second side including one or more electrical routing features having a second surface finish disposed on, and in direct contact with, the one or more electrical routing features, wherein the second surface finish has different chemical composition than the first surface finish and the second surface finish is affixed to the one or more I/O connection points or the one or more power connection points by solder.

12 . The package assembly of claim 11 , wherein the IC chip is a processor.

13 . The package assembly of claim 11 , further comprising one or more of an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, a Geiger counter, an accelerometer, a gyroscope, a speaker, or a camera coupled with the circuit board, wherein the package assembly is part of a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder.

Assignees

• Intel Corp

Inventors

• Zhang Qinglei

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/07236

  Soldering or alloying · CPC title

• H10W72/252

  comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W72/241

  Dispositions, e.g. layouts · CPC title

• H10W72/072

  of bump connectors · CPC title