Method of forming a temporary test structure for device fabrication

Patent metadata

Field	Value
Publication number	US-2018090399-A1
Application number	US-201715825193-A
Country	US
Kind code	A1
Filing date	Nov 29, 2017
Priority date	Aug 25, 2015
Publication date	Mar 29, 2018
Grant date	—

Abstract

A method of forming a temporary test structure for device fabrication is provided. The method allows for electrically testing conductive interconnects during controlled collapse chip connections (C4) fabrication and/or through-silicon vias (TSVs) during interposer fabrication. The method includes providing a substrate containing a plurality of electrically conductive interconnects extending vertically to top surface of the substrate. A temporary test structure is formed to connect the plurality of interconnects for electrical testing. Electrical testing is performed on the substrate by probing at different test locations on the temporary test structure. All or part of the temporary test structure is removed so as not to affect product performance. The temporary test structure can contain electrical test pads which provide a way to make temporary connections to small interconnect landings or features at extreme tight pitch to fan them out to testable pads sizes and pitches.

First claim

What is claimed is:

1 . A temporary test structure for testing conductive interconnections comprising:
a dielectric layer having a device side and a grind side; a plurality of electrically conductive interconnects extending vertically through the dielectric layer to a top surface of the device side; an insulating polymer covering the top surface except surfaces of the plurality of electrically conductive interconnects; a plurality of conformal electrical test structures, each formed on a surface of an electrically conductive interconnect and on a portion of the insulating polymer; and a plurality of controlled collapse chip connection (C4) bumps, each formed on a surface of a conformal electrical test structure; wherein one or more conformal electrical test structures further comprise an electrical test pad that extends past a sidewall of a C4 bump.

2 . The temporary test structure of claim 1 , wherein each of the conformal electrical test structures comprise a material selected from a group consisting of copper (Cu), titanium (Ti), tungsten (W), tantalum (Ta), ruthenium (Ru), chromium (Cr), iridium (Ir), osmium (Os), palladium (Pd), platinum (Pt), and alloys and ceramics thereof.

3 . The temporary test structure of claim 2 , wherein the material of the conformal electrical test structures comprises a titanium tungsten alloy (Ti-W) in a single layer, or comprises a copper (Cu) or Cu alloy over titanium or titanium tungsten alloy (Ti-W) in a bilayer.

4 . The temporary test structure of claim 1 , wherein a thickness of each of the conformal electrical test structures is in a range of about 20 nm to 1200 nm.

5 . A temporary test structure for testing through-silicon vias (TSVs) comprising:
a dielectric layer having a device side and a grind side; a plurality of TSVs extending vertically through the dielectric layer to a top surface of the device side and to a top surface of the grind side; a first insulating polymer covering the top surface of the device side except surfaces of the plurality of TSVs; a plurality of conformal, electrically conductive device side test structures, each formed on a surface of a TSV and on a portion of the first insulating polymer; a second insulating polymer covering the top surface of the grind side except surfaces of the plurality of TSVs; and a plurality of conformal, electrically conductive grind side test structures, each formed on a surface of a TSV and on a portion of the second insulating polymer.

6 . The temporary test structure of claim 5 , wherein each of the test structures comprises a material selected from a group consisting of copper (Cu), titanium (Ti), tungsten (W), tantalum (Ta), ruthenium (Ru), chromium (Cr), iridium (Ir), osmium (Os), palladium (Pd), platinum (Pt), and alloys and ceramics thereof.

7 . The temporary test structure of claim 6 , wherein the material of the test structures comprises a titanium tungsten alloy (Ti-W) in a single layer, or comprises a copper (Cu) or Cu alloy over titanium or titanium tungsten alloy (Ti-W) in a bilayer.

8 . The temporary test structure of claim 5 , wherein a thickness of each of the conformal electrical test structures is in a range of about 20 nm to 1200 nm.

9 . The temporary test structure of claim 5 , wherein a first device side test structure and a second device side test structure are electrically coupled by a conductive path.

10 . The temporary test structure of claim 9 , wherein the conductive path extends from the first device side test structure to a grind side test structure through a first TSV and from a grind side test structure to the second device side test structure through a second TSV.

11 . The temporary test structure of claim 8 , wherein the conductive path is capable of passing a test signal from the first device side test structure to the second device side test structure.

Assignees

• IBM

Inventors

• Arvin Charles L
• Erwin Brian Michael
• Maier Gary W

Classifications

• H10W72/952

  comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W72/29

  Bond pads specially adapted therefor · CPC title

• H10W72/247

  Dispositions of multiple bumps · CPC title

• H10W72/252

  comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W72/244

  relative to underlying supporting features, e.g. bond pads, RDLs or vias · CPC title