Polymer film stencil process for fan-out wafer-level packaging of semiconductor devices

Patent metadata

Field	Value
Publication number	US-2018063963-A1
Application number	US-201715689056-A
Country	US
Kind code	A1
Filing date	Aug 29, 2017
Priority date	Aug 29, 2016
Publication date	Mar 1, 2018
Grant date	—

Abstract

The present invention provides stencil-based processes for fan-out wafer-level packaging (“FOWLP”) that addresses the limitations associated with prior art over-molding of dies. In the inventive process, a temporary carrier is coated with a release layer and curable adhesive backing layer. A die stencil film is then laminated to the coated carrier, and the dies are placed inside pre-formed cavities created in the laminated stencil. The gaps between the dies and the stencil are filled with a curable polymeric material, and a redistribution layer is constructed according to conventional processes. This process results in better repeatability, lower bowing in the carrier, and enhanced downstream processing.

First claim

We claim:

1 . A fan-out wafer level package process comprising:
applying a stencil layer to a carrier stack, said stencil layer having openings formed therein, wherein said carrier stack comprises:
a carrier having an upper surface;
optionally a release layer adjacent the upper surface of said carrier, said release layer having an upper surface remote from said carrier; and
a bonding layer adjacent the upper surface of said release layer, if present, or adjacent the upper surface of said carrier if no release layer is present, said bonding layer having an upper surface remote from said carrier and said stencil layer being adjacent said bonding layer upper surface; and
placing dies in respective openings, said dies having respective lower surfaces adjacent said carrier stack and having respective upper surfaces remote from said carrier stack.

2 . The process of claim 1 , wherein said applying comprises placing a stencil comprising a free-standing body on said carrier stack to form said stencil layer.

3 . The process of claim 1 , wherein said applying comprises forming a polymer layer and openings in the polymer layer to yield said stencil layer.

4 . The process of claim 1 , wherein said placing comprises placing said dies in contact with said upper surface of said bonding layer.

5 . The process of claim 1 , wherein said stencil layer comprises a polymeric material selected from the group consisting of polycarbonates, polyetheretherketone, polyetherketone, polyethylene terephthalate, polyethylene naphthalate, polyimides, polyphenylene sulfide, polyphenylene oxide, polysulfone, polyethersulfones, and mixtures and/or copolymers of the foregoing.

6 . The process of claim 5 , wherein said stencil layer further comprises a particulate or fibrous filler.

7 . The process of claim 6 , wherein said filler is selected from the group consisting of carbon black, carbon fibers, graphite, silica, metal oxides, glass fibers, and mixtures thereof.

8 . The process of claim 1 , wherein said stencil layer comprises sidewalls defining each opening, and wherein said placing comprises positioning said dies so that gaps exist between said dies and said sidewalls.

9 . The process of claim 8 , further comprising filling said gaps with a gap-fill composition so as to form a layer of fan-out packages.

10 . The process of claim 9 , further comprising carrying out processing steps at said upper surfaces of said dies.

11 . The process of claim 10 , wherein said processing steps are selected from the group consisting of passivation, patterning, redistribution layer formation, singulation, electroplating, plasma etching, cleaning, chemical vapor deposition, physical vapor deposition, and combinations of the foregoing.

12 . The process of claim 11 , further comprising removing said carrier from said fan-out packages.

13 . The process of claim 9 , further comprising removing said carrier from said fan-out packages.

14 . The process of claim 13 , further comprising carrying out processing steps at said lower surfaces of said dies.

15 . The process of claim 14 , wherein said processing steps are selected from the group consisting of passivation, patterning, redistribution layer formation, singulation, electroplating, plasma etching, cleaning, chemical vapor deposition, physical vapor deposition, and combinations of the foregoing.

16 . The process of claim 1 , wherein said stencil layer is formed from a material other than pure silicon.

17 . A fan-out wafer level package structure comprising:
a carrier having an upper surface; optionally a release layer adjacent the upper surface of said carrier, said release layer having an upper surface remote from said carrier; a bonding layer adjacent the upper surface of said release layer, if present, or adjacent the upper surface of said carrier if no release layer is present, said bonding layer having an upper surface remote from said carrier; a stencil layer having openings formed therein and being adjacent said bonding layer upper surface; and dies in respective openings.

18 . The structure of claim 17 , wherein said stencil layer comprises a polymeric material selected from the group consisting of polycarbonates, polyetheretherketone, polyetherketone, polyethylene terephthalate, polyethylene naphthalate, polyimides, polyphenylene sulfide, polyphenylene oxide, polysulfone, polyethersulfones, and mixtures and/or copolymers of the foregoing.

19 . The structure of claim 18 , wherein said stencil layer further comprises a particulate or fibrous filler.

20 . The structure of claim 19 , wherein said filler is selected from the group consisting of carbon black, carbon fibers, graphite, silica, metal oxides, glass fibers, and mixtures thereof.

21 . The structure of claim 17 , wherein said stencil layer comprises sidewalls defining each opening, and said dies are positioned in said respective openings so that gaps exist between said dies and said sidewalls.

22 . The structure of claim 21 , further comprising a gap-fill composition in said gaps.

23 . The structure of claim 17 , wherein said dies have respective upper surfaces remote from said carrier, further comprising a redistribution layer adjacent at least some of said die upper surfaces.

24 . The structure of claim 17 , said stencil layer being formed from a material other than pure silicon.

25 . A fan-out wafer level package structure comprising a plurality of dies embedded in a polymeric layer, said dies having respective sidewalls, there being a layer of material between said sidewalls and said polymeric layer that is chemically different from the material of which said polymeric layer is formed.

26 . The structure of claim 25 , wherein said polymeric layer comprises a polymeric material selected from the group consisting of polycarbonates, polyetheretherketone, polyetherketone, polyethylene terephthalate, polyethylene naphthalate, polyimides, polyphenylene sulfide, polyphenylene oxide, polysulfone, polyethersulfones, and mixtures and/or copolymers of the foregoing.

27 . The structure of claim 26 , wherein said polymeric layer further comprises a particulate or fibrous filler.

28 . The structure of claim 27 , wherein said filler is selected from the group consisting of carbon black, carbon fibers, graphite, silica, metal oxides, glass fibers, and mixtures thereof.

29 . The structure of claim 25 , wherein said dies have respective upper and lower surfaces, and further comprising a redistribution layer adjacent at least one of said upper and lower surfaces.

30 . The structure of claim 29 , wherein a carrier is bonded to the other of said upper and lower surfaces.

31 . A fan-out wafer level package structure comprising a plurality of dies having upper and lower surfaces and being embedded in a non-epoxy polymeric layer, said dies having a redistribution layer adjacent at least one of said upper and lower surfaces.

32 . The structure of claim 31 , wherein said polymeric layer comprises a polymeric material selected from the group consisting of polycarbonates, polyetheretherketone, polyetherketone, polyethylene terephthalate, polyethylene naphthalate, polyimides, polyphenylene sulfide, polyphenylene oxide, polysulfone, polyethersulfones, and mixtures and/or copolyme

Assignees

• Brewer Science Inc

Inventors

• Flaim Tony D

Classifications

• H10W70/685

  comprising multiple insulating layers · CPC title

• H10W70/635

  Through-vias · CPC title

• H10W70/614

  the multiple chips being integrally enclosed · CPC title

• H10W70/611

  for connecting multiple chips together · CPC title

• H10W70/68 Primary

  Shapes or dispositions thereof · CPC title