Wafer-level package with enhanced performance

Patent metadata

Field	Value
Publication number	US-2018047653-A1
Application number	US-201715676621-A
Country	US
Kind code	A1
Filing date	Aug 14, 2017
Priority date	Aug 12, 2016
Publication date	Feb 15, 2018
Grant date	—

Abstract

The present disclosure relates to a packaging process to enhance thermal and electrical performance of a wafer-level package. The wafer-level package with enhanced performance includes a first thinned die having a first device layer, a multilayer redistribution structure, a first mold compound, and a second mold compound. The multilayer redistribution structure includes package contacts on a bottom surface of the multilayer redistribution structure and redistribution interconnects connecting the first device layer to the package contacts. The first mold compound resides over the multilayer redistribution structure and around the first thinned die, and extends beyond a top surface of the first thinned die to define a cavity within the first mold compound and over the first thinned die. The second mold compound fills the cavity and is in contact with the top surface of the first thinned die.

First claim

What is claimed is:

1 . A method comprising:
providing a mold wafer having a first die and a first mold compound, wherein:
the first die comprises a first device layer, a first dielectric layer over the first device layer, and a first silicon substrate over the first dielectric layer, wherein the first device layer comprises a plurality of first die contacts at a bottom surface of the first device layer;
a top surface of the first die is a top surface of the first silicon substrate and a bottom surface of the first die is the bottom surface of the first device layer; and
the first mold compound encapsulates the sides and the top surface of the first die, wherein the bottom surface of the first device layer is exposed;
forming a multilayer redistribution structure underneath the mold wafer, wherein:
the multilayer redistribution structure comprises a plurality of package contacts on a bottom surface of the multilayer redistribution structure and redistribution interconnects that connect the plurality of package contacts to certain ones of the plurality of first die contacts;
each of the plurality of package contacts is separate and surrounded by a continuous air gap, wherein the continuous air gap extends underneath the first die; and
connections between the redistribution interconnects and the plurality of first die contacts are solder-free;
forming a dielectric layer to fill the continuous air gap, wherein the dielectric layer has a planarized bottom surface; thinning down the first mold compound to expose the top surface of the first silicon substrate; removing substantially the first silicon substrate of the first die to provide a first thinned die and form a cavity within the first mold compound and over the first thinned die, wherein the first thinned die has a top surface exposed at a bottom of the cavity; and applying a second mold compound to substantially fill the cavity and directly contact the top surface of the first thinned die.

2 . The method of claim 1 wherein the first die provides a microelectromechanical systems (MEMS) component.

3 . The method of claim 1 wherein the first die is formed from a silicon-on-insulator (SOI) structure, wherein the first device layer of the first die is formed from a silicon epitaxy layer of the SOI structure, the first dielectric layer of the first die is a buried oxide layer of the SOI structure, and the first silicon substrate of the first die is a silicon substrate of the SOI structure.

4 . The method of claim 1 wherein the mold wafer further comprises a second intact die, which includes a second device layer, and a second silicon substrate over the second device layer, wherein:
a top surface of the second die is a top surface of the second silicon substrate and a bottom surface of the second die is the bottom surface of the second device layer;
the first die is taller than the second die; and
the first mold compound encapsulates the sides and the top surface of the second die, wherein the bottom surface of the second device layer is exposed.

5 . The method of claim 4 wherein the first die provides a MEMS component and the second intact die provides a complementary metal-oxide-semiconductor (CMOS) controller that controls the MEMS component.

6 . The method of claim 1 wherein the second mold compound has a thermal conductivity greater than 2 W/m·K.

7 . The method of claim 1 wherein the second mold compound has an electrical resistivity greater that 1 E6 Ohm-cm.

8 . The method of claim 1 wherein the first mold compound is formed from a same material as the second mold compound.

9 . The method of claim 1 wherein the first mold compound and the second mold compound are formed from different materials.

10 . The method of claim 1 wherein the top surface of the first thinned die exposed at the bottom of the cavity is a top surface of the first dielectric layer.

11 . The method of claim 1 wherein the multilayer redistribution structure is free of glass fiber.

12 . The method of claim 1 further comprising attaching the planarized bottom surface of the dielectric layer to a rigid carrier via an adhesive material before applying the second mold compound.

13 . The method of claim 12 further comprising detaching the rigid carrier from the dielectric layer after applying the second mold compound.

14 . The method of claim 1 wherein the dielectric layer encapsulates each of the plurality of package contacts.

15 . The method of claim 14 further comprising removing the dielectric layer to expose the plurality of package contacts after applying the second mold compound.

16 . The method of claim 1 wherein the dielectric layer encapsulates the sides of each of the plurality of package contacts, and the planarized bottom surface of the dielectric layer and a bottom surface of each of the plurality of package contacts are in a same flat plane.

17 . The method of claim 16 further comprising forming a bump directly over the bottom surface of each of the plurality of package contacts after applying the second mold compound.

18 . The method of claim 16 further comprising removing at least a portion of the dielectric layer after applying the second mold compound, such that at least portions of the sides of each of the plurality of package contacts are exposed.

19 . The method of claim 1 wherein the dielectric layer encapsulates the sides of each of the plurality of package contacts, and extends vertically beyond the bottom surface of each of the plurality of package contacts.

20 . The method of claim 19 wherein the dielectric layer extends underneath at least 70% of the first die.

21 . The method of claim 19 further comprising forming a plurality of external contacts, wherein each of the plurality of external contacts is in contact with a corresponding package contact through the dielectric layer and extends underneath the dielectric layer.

Assignees

• Qorvo Us Inc

Inventors

• Costa Julio C
• Hammond Jonathan Hale
• Vandemeer Jan Edward
• Hatcher Jr Merrill Albert
• Chadwick Jon

Classifications

• H10P14/6684

  the compound comprising silicon and oxygen · CPC title

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title

• H10W90/10

  Configurations of laterally-adjacent chips · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title