Power semiconductor device and method for manufacturing such a power semiconductor device

Patent metadata

Field	Value
Publication number	US-2018047652-A1
Application number	US-201715677625-A
Country	US
Kind code	A1
Filing date	Aug 15, 2017
Priority date	Aug 15, 2016
Publication date	Feb 15, 2018
Grant date	—

Abstract

A power semiconductor device is provided comprising a wafer, wherein in a termination region of the device a passivation layer structure is formed at least on a portion of a surface of the wafer and the passivation layer structure comprises in an order from the surface of the wafer in a direction away from the wafer a semi insulating layer, a silicon nitride layer, an undoped silicate glass layer and an organic dielectric layer. The silicon nitride layer has a layer thickness of at least 0.5 μm. The organic dielectric layer its attached to the undoped silicate glass layer and the undoped silicate glass layer is attached to the silicon nitride layer.

First claim

1 . A power semiconductor device comprising:
a wafer, wherein in a termination region of the device a passivation layer structure is formed at least on a portion of a surface of the wafer, the passivation layer structure comprises in an order from the surface of the wafer in a direction away from the wafer a semi-insulating layer, a silicon nitride layer, an undoped silicate glass layer and an organic dielectric layer, wherein the silicon nitride layer has a layer thickness of at least 0.5 μm, in that the organic dielectric layer is attached to the undoped silicate glass layer and in that the undoped silicate glass layer is attached to the silicon nitride layer.

2 . The power semiconductor device according to claim 1 , wherein the silicon nitride layer has a layer thickness of at least 0.7 μm.

3 . The power semiconductor device according to claim 1 , wherein the silicon nitride layer has a layer thickness of at most 2.0 μm.

4 . The power semiconductor device according to claim 1 , wherein the undoped silicate glass layer has a layer thickness of at least 0.4 μm.

5 . The power semiconductor device according to claim 1 , wherein the organic dielectric layer ( 17 ) includes at least one of a polyimide layer, a polybenzoxazole layer and a silicone layer.

6 . The power semiconductor device according to claim 1 , wherein the semi-insulating layer ( 13 ) is a semi-insulating polycrystalline silicon layer, an amorphous silicon layer, an amorphous silicon nitride or a diamond-like carbon layer.

7 . The power semiconductor device according to claim 1 , wherein the wafer is made of silicon or of a wide bandgap material or of silicon carbide.

8 . A method for manufacturing a power semiconductor device, the power semiconductor device comprising a wafer, the method comprising the following steps:
forming a passivation layer structure in a termination region of the device on at least a portion of a surface of the wafer, wherein the step of forming the passivation layer structure includes a step of forming a semi-insulating layer, a step of forming a silicon nitride layer on the semi-insulating layer, a step of forming an undoped silicate glass layer on the silicon nitride layer and a step of forming an organic dielectric layer on the undoped silicate glass layer, wherein the silicon nitride layer has a layer thickness of at least 0.5 μm and in that the organic dielectric layer is attached to the undoped silicate glass layer and in that the undoped silicate glass layer is attached to the silicon nitride layer.

9 . The method according to claim 8 , wherein the step of forming the silicon nitride layer includes a first step of forming a first silicon nitride layer at a temperature above 600° C. and a second step of forming a second silicon nitride layer at a temperature below 425° C.

10 . The method according to claim 9 , wherein forming the first silicon nitride layer by low pressure chemical vapour deposition.

11 . The method according to claim 9 , wherein forming the second silicon nitride layer by plasma enhanced chemical vapour deposition.

12 . The method according to claim 9 , wherein forming the second silicon nitride layer with a layer thickness of at least 0.5 μm.

13 . The method according to claim 8 , wherein forming the undoped silicate glass layer by plasma enhanced chemical vapour deposition at a temperature below 425° C.

14 . The method according to claim 8 , wherein selectively etching the silicon nitride layer and the undoped silicate glass layer ( 16 ) using a same masking layer.

15 . The power semiconductor device according to claim 1 , wherein the silicon nitride layer has a layer thickness of at least 0.9.

16 . The power semiconductor device according to claim 2 , wherein the silicon nitride layer has a layer thickness of at most 2.0 μm.

17 . The power semiconductor device according to claim 1 , wherein the undoped silicate glass layer has a layer thickness of at least 0.5 μm.

18 . The method according to claim 10 , wherein forming the second silicon nitride layer by plasma enhanced chemical vapour deposition.

19 . The method according to claim 10 , wherein forming the second silicon nitride layer with a layer thickness of at least 0.5 μm.

20 . The method according to claim 9 , wherein forming the undoped silicate glass layer by plasma enhanced chemical vapour deposition at a temperature below 425° C.

Assignees

• Abb Schweiz Ag

Inventors

• Papadopoulos Charalampos
• Rahimo Munaf

Classifications

• H10P14/69433

  the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz · CPC title

• H10P14/6905

  being a silicon carbide or silicon carbonitride and not containing oxygen, e.g. SiC or SiC:H · CPC title

• H10W74/147

  the encapsulations being multilayered · CPC title

• H10W42/00

  Arrangements for protection of devices (arrangements for thermal protection H10W40/00) · CPC title

• H10W74/137 Primary

  the encapsulations being directly on the semiconductor body (H10W74/134 takes precedence) · CPC title