Monolithic integration of iii-v cells for powering memory erasure devices

Patent metadata

Field	Value
Publication number	US-2018033906-A1
Application number	US-201715725742-A
Country	US
Kind code	A1
Filing date	Oct 5, 2017
Priority date	Jan 13, 2016
Publication date	Feb 1, 2018
Grant date	—

Abstract

A method for making a photovoltaic device is provided that includes the steps of providing a silicon substrate having a complementary metal-oxide semiconductor (“CMOS”); bonding a first layer of silicon oxide to a second layer of silicon oxide wherein the bonded layers are deposited on the silicon substrate; and forming a III-V photovoltaic cell on a side of the bonded silicon oxide layers opposite the silicon substrate, wherein when the III-V photovoltaic cell is exposed to radiation, the III-V photovoltaic cell generates a current that powers a memory erasure device to cause an alteration of a memory state of a memory cell in an integrated circuit.

First claim

What is claimed is:

1 . A photovoltaic device comprising:
a memory cell including:
a silicon substrate comprising a complementary metal-oxide semiconductor (“CMOS”); and
a first layer of silicon oxide bonded to a second layer of silicon oxide wherein the bonded layers are deposited on the silicon substrate;
a III-V photovoltaic cell on a side of the bonded silicon oxide layers opposite the silicon substrate; and a memory erasure device connected to the III-V photovoltaic cell, the III-V photovoltaic cell to generate a current when the III-V photovoltaic cell is exposed to radiation, the current to power the memory erasure device to cause an alteration of a memory state of the memory cell.

2 . The photovoltaic device of claim 1 wherein the photovoltaic device is formed from a single crystal chip.

3 . The photovoltaic device of claim 1 wherein the III-V photovoltaic cell comprises a Group III element selected from the group consisting of boron (B), aluminum (Al), gallium (Ga), indium (In), thallium (Tl), and ununtrium (Uut) and a Group V element selected from the group consisting of nitrogen (N), phosphorus (P), arsenic (As), antimony (Sb), bismuth (Bi) and ununpentium (Uup).

4 . The photovoltaic device of claim 1 wherein the memory erasure device comprises a reactive material comprising a thin metal film.

5 . The photovoltaic device of claim 4 wherein the current generated by the photovoltaic cell triggers an exothermic reaction in the reactive material.

6 . The photovoltaic device of claim 5 wherein a heat generated by the exothermic reaction in the reactive material alters the memory state of the memory cell.

7 . The photovoltaic device of claim 1 wherein the memory erasure device comprises nickel, aluminum, titanium, copper, palladium, boron, platinum, copper oxide, hafnium oxide, or combinations thereof.

8 . The photovoltaic device of claim 1 wherein the III-V photovoltaic cell comprises a thin III-V layer and an epitaxially grown III-V layer.

9 . A photovoltaic device comprising:
a III-V wafer comprising an epitaxial template layer; oxide trenches; a III-V photovoltaic cell; and a transparent conducting layer.

10 . A photovoltaic device, comprising:
a silicon substrate comprising a complementary metal-oxide semiconductor (“CMOS”); a first layer of silicon oxide bonded to a second layer of silicon oxide wherein the bonded layers are deposited on the silicon substrate; and a III-V photovoltaic cell on a side of the bonded silicon oxide layers opposite the silicon substrate, wherein when the III-V photovoltaic cell is exposed to radiation, the III-V photovoltaic cell generates a current that powers a memory erasure device to cause an alteration of a memory state of a memory cell in an integrated circuit.

11 . The photovoltaic device of claim 10 wherein the photovoltaic device is a monolithic single crystal chip.

12 . The photovoltaic device of claim 10 wherein the III-V photovoltaic cell comprises a Group III element selected from the group consisting of boron (B), aluminum (Al), gallium (Ga), indium (In), thallium (Tl), and ununtrium (Uut) and a Group V element selected from the group consisting of nitrogen (N), phosphorus (P), arsenic (As), antimony (Sb), bismuth (Bi) and ununpentium (Uup).

13 . The photovoltaic device of claim 10 wherein the memory erasure device comprises a reactive material comprising a thin metal film.

14 . The photovoltaic device of claim 13 wherein the current generated by the photovoltaic cell triggers an exothermic reaction in the reactive material.

15 . The photovoltaic device of claim 14 wherein a heat generated by the exothermic reaction in the reactive material alters the memory state of the memory cell.

16 . The photovoltaic device of claim 10 wherein the memory erasure device comprises nickel, aluminum, titanium, copper, palladium, boron, platinum, copper oxide, hafnium oxide, or combinations thereof.

17 . The photovoltaic device of claim 10 wherein the memory cell comprises a phase change memory.

18 . The photovoltaic device of claim 10 wherein the III-V photovoltaic cell comprises a thin III-V layer and an epitaxially grown III-V layer.

19 . The photovoltaic device of claim 10 wherein the III-V photovoltaic cell is in electrical contact with the CMOS.

20 . The photovoltaic device of claim 10 wherein the III-V photovoltaic cell is in electrical contact with the memory erasure device.

Assignees

• IBM

Inventors

• Rodbell Kenneth
• Shahrjerdi Davood

Classifications

• H10W42/40 Primary

  protecting against tampering, e.g. unauthorised inspection or reverse engineering · CPC title

• Y02E10/544

  Solar cells from Group III-V materials · CPC title

• G06F2221/2143

  Clearing memory, e.g. to prevent the data from being stolen · CPC title

• G06F21/87 Primary

  by means of encapsulation, e.g. for integrated circuits · CPC title

• H01L27/1443

  Electricity · mapped topic