Semiconductor device having a rib structure and manufacturing method of the same

Patent metadata

Field	Value
Publication number	US-2018033772-A1
Application number	US-201715730256-A
Country	US
Kind code	A1
Filing date	Oct 11, 2017
Priority date	Dec 15, 2015
Publication date	Feb 1, 2018
Grant date	—

Abstract

A semiconductor device is provided. The semiconductor device includes at least one first die, a rib structure enclosing the at least one first die, and a molding layer covering the at least one first die. The rib structure is formed of a first material and the molding layer is formed of a second material. A Young's modulus of the first material is larger than a Young's modulus of the second material. The rib structure includes a through hole, and the through hole is filled with a conductive material.

First claim

What is claimed is:

1 . A semiconductor device, comprising:
at least one first die; a rib structure enclosing the at least one first die and formed of a first material; and a molding layer covering the at least one first die and formed of a second material; wherein a Young's modulus of the first material is larger than a Young's modulus of the second material, wherein the rib structure includes a through hole, and the through hole is filled with a conductive material.

2 . The semiconductor device according to claim 1 , wherein the first material is silicon, metal, metal alloy, or ceramic material.

3 . The semiconductor device according to claim 1 , wherein the at least one first die comprises a plurality of first dies, and the rib structure encloses the first dies.

4 . The semiconductor device according to claim 1 , further comprising:
a second die adjacent to the at least one first die; wherein the rib structure separates the at least one first die from the second die.

5 . The semiconductor device according to claim 1 , wherein the conductive material is indium tin oxide, metal or metal alloy.

6 . The semiconductor device according to claim 1 , further comprising:
a redistribution layer electrically connected to the at least one first die; and a plurality of solder balls electrically connected to the redistribution layer.

7 . The semiconductor device according to claim 6 , further comprising:
a dielectric layer disposed under the at least one first die; wherein the redistribution layer is disposed in the dielectric layer.

8 . The semiconductor device according to claim 6 , further comprising:
a dielectric layer disposed on the molding layer; wherein the redistribution layer is disposed in the dielectric layer.

9 . The semiconductor device according to claim 1 , wherein a top surface of the molding layer and a top surface of the rib structure are coplanar.

10 . The semiconductor device according to claim 1 , wherein the rib structure is formed of a plurality of first ribs and second ribs intersecting the first ribs, and an extending direction of the first ribs is different from an extending direction of the second ribs.

11 . A semiconductor stacked structure comprising a plurality of semiconductor devices stacked together, each of the semiconductor devices comprising:
at least one first die; a rib structure enclosing the at least one first die and formed of a first material; a molding layer covering the at least one first die and formed of a second material; a redistribution layer electrically connected to the at least one first die; and a plurality of solder balls electrically connected to the redistribution layer; wherein a Young's modulus of the first material is larger than a Young's modulus of the second material, and the semiconductor devices are electrically connected to each other by the rib structure, the redistribution layer and the solder balls, wherein the rib structure includes a through hole, and the through hole is filled with a conductive material.

12 . A method of manufacturing a semiconductor device, comprising:
forming a first adhesive tape on a carrier; forming a rib structure and at least one first die on the first adhesive tape, wherein the rib structure encloses the at least one first die; forming a through hole in the rib structure; filling the through hole with a conductive material; forming a molding layer on the at least one first die, wherein spaces between the at least one first die and the rib structure are filled with the molding layer; curing the molding layer; removing the first adhesive tape and the carrier; and forming a redistribution layer and a plurality of solder balls electrically connected to the at least one first die; wherein the rib structure is formed of a first material, the molding layer is formed of a second material, and a Young's modulus of the first material is larger than a Young's modulus of the second material.

13 . The method according to claim 12 , further comprising:
forming a cover layer on the rib structure and the molding layer by a second adhesive tape before removing the first adhesive tape and the carrier; post curing the molding layer; and removing the second adhesive tape and the cover layer.

14 . The method according to claim 12 , further comprising:
forming a first dielectric layer, such that the rib structure and the at least one first die are formed on the first dielectric layer, wherein the redistribution layer is formed on the first dielectric layer and opposite to the at least one first die; and forming a second dielectric layer, such that the redistribution layer is formed between the first dielectric layer and the second dielectric layer.

15 . The method according to claim 14 , wherein the first dielectric layer comprises a plurality of holes, and the redistribution layer is electrically connected to the at least one first die by the holes.

16 . The method according to claim 14 , wherein the second dielectric layer comprises a plurality of holes, and the solder balls are electrically connected to the redistribution layer by the holes.

17 . The method according to claim 12 , further comprising:
forming a plurality of holes on the molding layer, such that the holes expose an electrode of the at least one first die; and forming the redistribution layer on the molding layer, wherein the redistribution layer is electrically connected to the at least one first die by the hole.

Assignees

• Ind Tech Res Inst

Inventors

• Shen Chih-Ming
• Wu Shih-Hsien
• Dai Ming-Ji

Classifications

• H10P72/7402

  Wafer tapes, e.g. grinding or dicing support tapes · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/291

  characterised by containers, encapsulations, or other housings for the stacked chips · CPC title

• H10W90/10

  Configurations of laterally-adjacent chips · CPC title