Apparatus for data retention and supply noise mitigation using clamps

Patent metadata

Field	Value
Publication number	US-2018024761-A1
Application number	US-201715706521-A
Country	US
Kind code	A1
Filing date	Sep 15, 2017
Priority date	May 10, 2016
Publication date	Jan 25, 2018
Grant date	—

Abstract

An apparatus is provided which comprises: a first power gate transistor coupled to an ungated power supply node and a gated power supply node, the first power gate transistor having a gate terminal controllable by a first logic; and a second power gate coupled to the ungated power supply node and the gated power supply node, the second power gate transistor having a gate terminal controllable by a second logic, wherein the first power gate transistor is larger than the second power gate transistor, and wherein the second logic is operable to: weakly turn on the second power gate, fully turn on the second power gate, turn off the second power gate, and connecting the second power gate as diode.

First claim

We claim:

1 . An apparatus comprising:
a first power gate transistor coupled to an ungated power supply node and a gated power supply node; and a second power gate transistor coupled to the ungated power supply node and the gated power supply node, wherein the second power gate transistor is operable to be tuned on such that it is diode-connected between the gated and ungated power supply nodes.

2 . The apparatus of claim 1 , wherein first power gate transistor is larger in size than the second power gate transistor.

3 . The apparatus of claim 1 , wherein the second power gate transistor is operable by a circuitry which comprises transistors which are collectively smaller in size than a size of the second power gate.

4 . The apparatus of claim 3 , wherein the circuitry comprises a first p-type transistor coupled to the gate terminal of the second power gate transistor and the ungated power supply node.

5 . The apparatus of claim 4 , wherein the circuitry comprises a second p-type transistor coupled in series with the first p-type transistor, and coupled to the gate terminal of the second power gate transistor and the gated power supply node.

6 . The apparatus of claim 5 , wherein the circuitry comprises a third p-type-transistor coupled to a gate terminal of the first p-type transistor and the gate terminal of the second power gate transistor.

7 . The apparatus of claim 3 , wherein the circuitry is to operate in one or several modes including:
a first mode to weakly turn on the second power gate transistor, a second mode to substantially turn on the second power gate transistor, and a third mode to turn off the second power gate transistor.

8 . An apparatus comprising:
a first power gate transistor coupled to a gated power supply node and an ungated power supply node; a first circuitry coupled to a gate terminal of the first power gate transistor, the first circuitry comprising a first transistor of a first conductivity type and a second conductor of a second conductivity type coupled in series with the first transistor, wherein gate terminals of the first and second transistors of the first circuitry are controllable by separate nodes; a second power gate transistor coupled to the gated and ungated power supply nodes; and a second circuitry coupled to the second power gate transistor, wherein the second circuitry is to weakly turn on the second power gate transistor.

9 . The apparatus of claim 8 , wherein the second circuitry comprises devices which are collectively smaller in size than a size of the second power gate transistor.

10 . The apparatus of claim 8 , wherein the second circuitry is to substantially turn on the second power gate transistor during a first mode, and to substantially turn off the second power gate transistor during a second mode.

11 . An apparatus comprising:
an ungated power supply node; a gated power supply node; and a power gate transistor coupled to the ungated power supply node and the gated power supply node, wherein the power gate transistor is operable to be tuned on such that it is diode-connected between the gated and ungated power supply nodes.

12 . The apparatus of claim 11 comprises a second power gate transistor coupled to the ungated power supply node and the gated power supply node, wherein the second power gate is larger in size than the power gate transistor.

13 . The apparatus of claim 12 , wherein the second power gate transistor is controllable by a circuitry comprising a first transistor of first conductivity type and a second conductor of a second conductivity type coupled in series with the first transistor, and wherein gate terminals of the first and second transistors of the circuitry are controllable by separate nodes.

14 . The apparatus of claim 11 comprises a circuitry to control the power gate transistor to cause the power gate transistor to weakly turn on.

15 . The apparatus of claim 11 comprises a circuitry which is operable to diode-connect a device coupled to a gate of the second power gate transistor.

16 . The apparatus of claim 11 , wherein the power gate transistor is controllable by a circuitry which has a total size smaller than a size of the power gate transistor.

17 . The apparatus of claim 11 , comprises a circuitry which is operable to weakly turn on the power gate transistor such that at least two diodes are formed between the ungated power supply node and the gated power supply node.

18 . The apparatus of claim 11 , comprises a circuitry which is operable to substantially turn on the power gate transistor during a first mode, and wherein the circuitry is operable to fully turn off the power gate transistor during a second mode different from the first mode.

19 . The apparatus of claim 18 , wherein the first mode is a normal active mode.

20 . The apparatus of claim 18 , wherein the second mode is a destructive sleep mode.

Assignees

• Intel Corp

Inventors

• Meinerzhagen Pascal A
• Kim Stephen T
• Thaploo Anupama A
• Khellah Muhammad M

Classifications

• G11C5/148 Primary

  Details of power up or power down circuits, standby circuits or recovery circuits · CPC title

• G06F3/0659

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

• G06F3/0685

  Hybrid storage combining heterogeneous device types, e.g. hierarchical storage, hybrid arrays · CPC title

• G06F3/0625

  Power saving in storage systems · CPC title

• G06F3/0619 Primary

  in relation to data integrity, e.g. data losses, bit errors · CPC title