Charge-saving power-gate apparatus and method

Patent metadata

Field	Value
Publication number	US-9966940-B2
Application number	US-201113976156-A
Country	US
Kind code	B2
Filing date	Sep 23, 2011
Priority date	Sep 23, 2011
Publication date	May 8, 2018
Grant date	May 8, 2018

Abstract

A power-gate circuit includes a power-gate transistor operable to switch to decouple a first supply voltage from a second supply voltage during an idle mode, and to couple the first supply voltage to the second supply voltage during a full operational mode. Part of the charge stored at a gate terminal of the power-gate transistor, would have been otherwise flushed to ground while turning on the power-gate transistor, is routed to the rail of the second supply voltage of the logic block. Part of the charge on the rail of the second supply voltage is used to charge the gate terminal of the power-gate transistor to deactivate the power-gate transistor if the logic block goes to the idle mode. Energy is saved both ways because of the charge recycling and the ability to use the power gate circuit even in cases where the duration of the idle mode may be short.

First claim

What is claimed is:

1. An apparatus, comprising:
a power-gate transistor configured to transition to a first state to decouple a first supply voltage from a second supply voltage, and configured to transition to a second state to couple the first supply voltage to the second supply voltage, wherein the power-gate transistor includes a control terminal, a first terminal coupled to the first supply voltage, and a second terminal coupled to the second supply voltage; and
a switch transistor coupled between the control terminal of the power-gate transistor and the second supply voltage;
wherein, to transition the power-gate transistor from the second state to the first state, the switch transistor is responsive to a signal to close for a first-pre-defined time period to transition the power-gate transistor to the first state, and then responsive to the signal to open after the first pre-defined time period, while the power-gate transistor remains in the first state; and
wherein, to transition the power-gate transistor from the first state to the second state, the switch transistor is responsive to the signal to close for a second pre-defined time period to enable charge to flow from the control terminal of the power-gate transistor to the second supply voltage to transition the power-gate transistor to the second state and then responsive to the signal to open after the second pre-defined time period, while the power-gate transistor remains in the second state.

2. The apparatus of claim 1 wherein, to transition the power-gate transistor from the second state to the first state, the switch transistor is responsive to the signal to close to enable charge to flow from the second supply voltage to the control terminal of the power-gate transistor to transition the power-gate transistor to the first state.

3. The apparatus of claim 1 wherein the power-gate transistor includes a P-type transistor.

4. The apparatus of claim 1 , further comprising:
a first transistor having a first terminal coupled to the first supply voltage, a second terminal coupled to the control terminal of the power-gate transistor, and a third terminal coupled to receive a first control signal that is different from the signal to which the switch transistor is responsive; and
a second transistor having a first terminal coupled to the second terminal of the first transistor and to the control terminal of the power-gate transistor, a second terminal coupled to ground, and a third terminal coupled to receive a second control signal that is different from the first control signal.

5. The apparatus of claim 4 wherein the signal to which the switch transistor is responsive is a third control signal;
wherein, to transition the power-gate transistor from the second state to the first state:
the second control signal transitions, at a first time, from a first level to a second level to deactivate the second transistor, and the third control signal transitions from the second level to the first level to close the switch transistor;
the third control signal transitions, at a second time the first pre-defined time period after the first time, from the first level to the second level to open the switch transistor; and
the first control signal transitions, at the second time, from the first level to the second level to activate the first transistor and to keep the power-gate transistor deactivated to maintain the first supply voltage decoupled from the second supply voltage; and

wherein, to transition the power-gate transistor from the first state to the second state:
the first control signal transitions, at a third time, from the second level to the first level to deactivate the first transistor;
the third control signal transitions, at the third time, from the second level to the first level to close the switch transistor;
the third control signal transitions, at a fourth time the second pre-defined time period after the third time, from the first level to the second level to open the switch transistor; and
the second control signal transitions, at the fourth time, from the second level to the first level to activate the second transistor and to keep the power-gate transistor activated to maintain the first supply voltage coupled to the second supply voltage.

6. The apparatus of claim 5 wherein the first, second, and third control signals include voltage signals, and wherein the first level is a higher voltage level relative to the second level.

7. The apparatus of claim 4 wherein the first transistor includes a P-type transistor and wherein the second transistor includes an N-type transistor.

8. A method, comprising:
transitioning a power-gate transistor of a power-gate circuit to a first state to decouple a first supply voltage from a second supply voltage;
transitioning the power-gate transistor to a second state to couple the first supply voltage to the second supply voltage; and
operating a switch transistor coupled between a control terminal of the power-gate transistor and the second supply voltage;
wherein said operating, for transitioning the power-gate transistor to the first state, includes the switch transistor being responsive to a signal to close for a first pre-defined time period to enable charge to flow from the second supply voltage to the control terminal of the power-gate transistor to transition the power-gate transistor to the first state, and then responsive to the signal to open after the first pre-defined time period, while the power-gate transistor remains in the first state; and
wherein said operating, for transitioning the power-gate transistor to the second state, includes the switch transistor being responsive to a signal to close for a second pre-defined time period to enable charge to flow to the second supply voltage from the control terminal of the power-gate transistor to transition the power-gate transistor to the second state, and then responsive to the signal to open after the second pre-defined time period, while the power-gate transistor remains in the second state.

9. The method of claim 8 wherein said transitioning the power-gate transistor to the first state includes deactivating a P-type transistor so as to operate as an open circuit between the first supply voltage and the second supply voltage, and wherein said transitioning the power-gate transistor to the second state includes activating the P-type transistor so as to operate as a short circuit between the first supply voltage and the second supply voltage.

10. The method of claim 8 wherein the power-gate circuit includes a first transistor controlled by a first signal and a second transistor controlled by a second signal, and wherein the signal to which the switch transistor is responsive is a third signal, the method further comprising:
for transitioning the power-gate transistor to the first state:
at a first time, transitioning the second signal from a first level to a second level to deactivate the second transistor, and transitioning the third signal from the second level to the first level to close the switch transistor; and
at a second time the first pre-defined time period after the first time, transitioning the third signal from the first level to the second level to open the switch transistor, and transitioning the first signal from the first level to the second level to activate the first transistor and to keep the power-gate transistor deactivated to maintain the first supply voltage decoupled from the second supply voltage;

for transitioning the power-gate transistor to the second state:
at a third time, transitioning the first signal from the second level to the first level to deactivate the first transistor, and transitioning

Assignees

• Rotem Shai
• Unger Norbert
• Zelikson Michael
• Intel Corp

Inventors

• Rotem Shai
• Unger Norbert
• Zelikson Michael

Classifications

• H03K17/687 Primary

  the devices being field-effect transistors · CPC title

• H03K2217/0063

  High side switches, i.e. the higher potential [DC] or life wire [AC] being directly connected to the switch and not via the load · CPC title

• H03K2217/0036

  Means reducing energy consumption · CPC title

• H03K17/00 Primary

  Electronic switching or gating, i.e. not by contact-making and –breaking (gated amplifiers H03F3/72; switching arrangements for exchange systems using static devices H04Q3/52) · CPC title