Integrated circuit structure

Patent metadata

Field	Value
Publication number	US-2018024191-A1
Application number	US-201715584971-A
Country	US
Kind code	A1
Filing date	May 2, 2017
Priority date	Jul 19, 2016
Publication date	Jan 25, 2018
Grant date	—

Abstract

An integrated circuit structure including a reference circuit and at least two core circuits is provided. The reference circuit provides a reference current. The at least two core circuits are coupled to the reference circuit for receiving the reference current. Each of the core circuits includes a current-calibration circuit. The current-calibration circuit generates a bias current according to the reference current in the core circuit. The core circuits use the bias current to replace the reference circuit. In an IC test process, the reference circuit provides the reference current through the pin of the integrated circuit electronically connected to the external impedance. After the IC test process, the connection of the reference circuit and the pin of the integrated circuit is disconnected.

First claim

What is claimed is:

1 . An integrated circuit structure, comprising:
a reference circuit, generating a reference current; and at least two core circuits, coupled to the reference circuit for receiving the reference current, wherein each of the core circuits comprises: a current-calibration circuit, generating a bias current according to the reference current, the core circuit uses the bias current as reference so as to replace the reference current which generated by the reference circuit, wherein in an IC test process, the reference circuit is electrically connected to an external impedance through a pin of the integrated circuit structure to generate the reference current, and after the IC test process, a connection between the reference circuit and the pin of the integrate circuit structure is disconnected.

2 . The integrated circuit structure as claimed in claim 1 , wherein the current-calibration circuit comprises:
a voltage generator, configured to generate an internal reference voltage; a current generator, coupled to the voltage generator, and generating an internal reference current according to the internal reference voltage; a digital-control current mirror, coupled to the current generator, and generating a calibrating current according to the internal reference current; and a current comparator, coupled to the digital-control current mirror, and configured to compare the reference current with the calibrating current, wherein when the current-calibration circuit is activated, the digital-control current mirror adjusts a current value of the calibrating current, the digital-control current mirror generates the bias current according to a comparison result of the current comparator, wherein a current value of the bias current is substantially the same as a present current value of the reference current.

3 . The integrated circuit structure as claimed in claim 2 , wherein the internal reference voltage is proportional to an absolute temperature, and
the current generator comprises an impedance device having a positive temperature coefficient, and the current generator generates the internal reference current that is independent to a variation of the absolute temperature and a variation of a system voltage according to the internal reference voltage.

4 . The integrated circuit structure as claimed in claim 3 , further comprising a memory corresponding to each of the current-calibration circuits, the memory is configured to record a calibrated current value of the calibrated bias current.

5 . The integrated circuit structure as claimed in claim 4 , wherein the reference circuit comprises a reference current generator,
wherein in the IC test process, the reference current generator of the integrated circuit structure is coupled to the external impedance through the pin of the integrated circuit structure to generate the reference current, and the current-calibration circuit generates the bias current in the at least one core circuit according to the reference current, and record a calibrated current value of the bias current in the memory, wherein the current-calibration circuit generates the bias current according to the calibrated current value recorded by the memory.

6 . The integrated circuit structure as claimed in claim 1 , further comprising a memory, and
the reference circuit comprising: a reference current generator, configured to generate a first current; and a second current-calibration circuit, coupled to the reference current generator, wherein the second current-calibration circuit uses the memory to record a calibrated current value of the first current, and generates the reference current according to the recorded calibrated current value.

7 . The integrated circuit structure as claimed in claim 6 , wherein in the IC test process, the reference current generator is coupled to the external impedance through the pin of the integrated circuit structure to generate the first current, and the second current-calibration circuit records the calibrated current value of the first current,
the current-calibration circuit generates the bias current according to the reference current generated by the second current-calibration circuit.

8 . The integrated circuit structure as claimed in claim 1 , further comprising:
a distribution-current mirror, coupled between the reference circuit and the at least two core circuits, the distribution-current mirror configured to receive the reference current and to generate a plurality of mirror-mapping currents to the core circuits to serve as the reference current of the core circuits respectively.

9 . The integrated circuit structure as claimed in claim 1 , further comprising:
a multiplexer, having a first connection terminal coupled to the reference circuit, a second connection terminal coupled to a digital circuit in the integrated circuit structure, and an output connection terminal coupled to the pin of the integrated circuit structure, wherein a portion of the pin which expose outside the integrated circuit structure is electrically connected to the external impedance, wherein in the IC test process, the multiplexer electrically connects the first connection terminal to the output connection terminal, and after the IC test process, the multiplexer electrically connects the second connection terminal to the output connection terminal.

Assignees

• Ali Corp

Inventors

• Chen Chi-Bin

Classifications

• G05F3/00 Primary

  Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties {(current generators specially designed for use in phase-locked loops H03L7/0891)} · CPC title

• G01R17/02

  Arrangements in which the value to be measured is automatically compared with a reference value · CPC title

• G01R31/31915

  In-circuit Testers · CPC title

• G01R35/04

  of instruments for measuring time integral of power or current · CPC title

• G01R31/3191 Primary

  Calibration · CPC title