Digitally trimmable integrated resistors including resistive memory elements

Patent metadata

Field	Value
Publication number	US-10347309-B2
Application number	US-201715439800-A
Country	US
Kind code	B2
Filing date	Feb 22, 2017
Priority date	Jun 25, 2015
Publication date	Jul 9, 2019
Grant date	Jul 9, 2019

Abstract

Embodiments include a resistor, coupled on a signal path, that includes one or more resistive memory elements, such as one or more magnetic tunnel junctions (MTJs). The resistance of the resistive memory elements may be digitally trimmable to adjust a resistance of the resistor on the signal path. The resistor may be incorporated into an analog or mixed signal circuit to pass an analog signal on the signal path. Other embodiments may be described and claimed.

First claim

What is claimed is:

1. A circuit comprising:
one or more circuit elements to process an analog signal on a signal path; and
a resistor coupled along the signal path to pass the analog signal along the signal path through the resistor, the resistor including a plurality of resistor cells coupled to one another in a series-parallel combination, and individual resistor cells of the plurality of resistor cells including one or more resistive elements that are switchable between two or more resistance states, wherein respective resistances of individual resistor cells of the plurality of resistor cells are digitally adjustable, responsive to one or more digital control signals, to adjust an overall resistance of the resistor;
wherein the one or more digital control signals are distinct from the analog signal.

2. The circuit of claim 1 , wherein the individual resistive elements include a magnetic tunnel junction (MTJ) element.

3. The circuit of claim 2 , wherein the MTJ element is coupled on the signal path and includes a free layer and a pinned layer, wherein the one or more digital control signals include a source line signal, a bit line signal, and a word line signal, and wherein the individual resistor cells include:
a source line to receive the source line signal;
a bit line to receive the bit line signal;
a word line to receive the word line signal;
a first transistor coupled between the source line and the signal path adjacent the pinned layer of the MTJ element, a gate terminal of the first transistor coupled to the word line; and
a second transistor coupled between the bit line and the signal path adjacent the free layer of the MTJ element, a gate terminal of the second transistor coupled to the word line;
wherein the source line, bit line, and word line are different from the signal path.

4. The circuit of claim 1 , wherein the resistor is not part of a memory circuit and the individual resistive elements are not used to store data.

5. The circuit of claim 1 , wherein the individual resistive elements include a conducting bridge random access memory (CBRAM) resistive element, a phase change random access memory (PCRAM) resistive element, or a resistive random access memory (RRAM) resistive element.

6. The circuit of claim 1 , wherein the resistor is disposed in one or more upper metal layers of the circuit that are above an active substrate region of the circuit.

7. The circuit of claim 1 , wherein the circuit is a digital-to-analog conversion (DAC) circuit or an analog-to-digital conversion (ADC) circuit.

8. The circuit of claim 1 , wherein the circuit is a biasing circuit, an input/output circuit, or a radio frequency circuit.

9. A circuit comprising:
circuitry including a signal path; and
a resistor coupled on the signal path to pass a signal along the signal path through the resistor, the resistor including:
a magnetic tunnel junction (MTJ) element coupled on the signal path, the MTJ element including a free layer and a pinned layer;
a source line to receive a source line signal;
a bit line to receive a bit line signal;
a first transistor coupled between the source line and the signal path adjacent the pinned layer of the MTJ element; and
a second transistor coupled between the bit line and the signal path adjacent the free layer of the MTJ element;
wherein the source line, bit line, and word line are different from the signal path.

10. The circuit of claim 9 , further comprising a word line to receive a word line signal, wherein a gate terminal of the first transistor and a gate terminal of the second transistor are coupled to the word line to receive the word line signal.

11. The circuit of claim 10 , wherein, when the word line signal has a first value, the MTJ element is switchable between a first resistance and a second resistance based on a value of the source line signal and a value of the bit line signal.

12. The circuit of claim 10 , wherein the MTJ element is a first MTJ element, the word line is a first word line, and the word line signal is a first word line signal, and wherein the resistor further includes:
a second MTJ element coupled on the signal path;
a second word line to receive a second word line signal;
a third transistor coupled between the source line and the signal path adjacent to a pinned layer of the second MTJ element, a gate terminal of the third transistor coupled to the second word line; and
a fourth transistor coupled between the bit line and the signal path adjacent to a free layer of the second MTJ element, a gate terminal of the fourth transistor coupled to the second word line.

13. The circuit of claim 9 , wherein the MTJ element, first transistor, and second transistor are included in a first resistor cell of the resistor, and wherein the resistor includes a plurality of resistor cells, including the first resistor cell, coupled in a series-parallel combination.

14. The circuit of claim 9 , wherein the signal is an analog signal.

15. The circuit of claim 9 , wherein the circuit is a radio frequency circuit.

16. The circuit of claim 9 , wherein the circuit is a digital-to-analog conversion (DAC) circuit, an analog-to-digital conversion (ADC) circuit, a biasing circuit, or an input/output circuit.

17. The circuit of claim 10 , further comprising a calibration circuit to control the bit line signal, the source line signal, and the word line signal to adjust a resistance of the resistor.

18. The circuit of claim 9 , further comprising a passive resistor coupled in series with the MTJ element on the signal path, wherein a resistance of the passive resistor is greater than a maximum resistance of the MTJ element.

19. A computer system comprising:
a memory;
a processor coupled to the memory; and
circuitry coupled to the processor and separate from the memory, the circuitry including a series-parallel combination of magnetic tunnel junction (MTJ) elements to form a resistor coupled along a signal path to pass an analog signal on the signal path through the MTJ elements.

20. The system of claim 19 , wherein the MTJ elements are included in respective resistor cells of the resistor and include a first MTJ element included in a first resistor cell of the resistor, and wherein the first resistor cell further includes:
a source line to receive a source line signal;
a bit line to receive a bit line signal;
a word line to receive a word line signal;
a first transistor coupled between the source line and the signal path adjacent a pinned layer of the first MTJ element, a gate terminal of the first transistor coupled to the word line; and
a second transistor coupled between the bit line and the signal path adjacent a free layer of the first MTJ element, a gate terminal of the second transistor coupled to the word line;
wherein the source line, bit line, and word line are different from the signal path.

21. The system of claim 20 , wherein, when the word line signal has a first value, the first MTJ element is switchable between a first resistance and a second resistance based on a value of the source line signal and a value of the bit line signal.

22. The system of claim 20 , further comprising a calibration circuit coupled to the resistor to control the bit line signal, the source line signal, and the word line signal to adjust a resistance of the resistor.

23. The system of claim 22 , wherein the circuit is a radio frequency circuit, a digital-to-analog conversion (DAC) circuit, an analog

Assignees

• Intel Corp

Inventors

• Kulkarni Jaydeep P
• Ravi Ashoke
• Somasekhar Dinesh
• Balamurugan Ganesh
• Shekhar Sudip
• Musah Tawfiq
• Hsueh Tzu-Chien

Classifications

• G11C11/1673

  Reading or sensing circuits or methods · CPC title

• H03K3/356104

  using complementary field-effect transistors (H03K3/35625 takes precedence) · CPC title

• H04L25/03878

  Line equalisers; line build-out devices · CPC title

• G11C11/1675

  Writing or programming circuits or methods · CPC title

• H04L25/00

  Baseband systems · CPC title