Tunneling transistor and method of fabricating the same

Patent metadata

Field	Value
Publication number	US-2018019341-A1
Application number	US-201615213370-A
Country	US
Kind code	A1
Filing date	Jul 18, 2016
Priority date	Jul 18, 2016
Publication date	Jan 18, 2018
Grant date	—

Abstract

A tunneling transistor and a method of fabricating the same, the tunneling transistor includes a fin shaped structure, a source structure and a drain structure, and a gate structure. The fin shaped structure is disposed in a substrate, and the source structure and the drain structure are disposed the fin shaped structure, wherein an entirety of the source structure and an entirety of the drain structure being of complementary conductivity types with respect to one another and having different materials. A channel region is disposed in the fin shaped structure between the source structure and the drain structure and the gate structure is disposed on the channel region. That is, a hetero tunneling junction is vertically formed between the channel region and the source structure, and between the channel region and the drain structure in the fin shaped structure.

First claim

1 . A method of forming a tunneling transistor, comprising:
forming a fin shaped structure in a substrate; forming a gate structure across the fin shaped structure; forming two recesses at two sides of the gate structure in the fin shaped structure, wherein each of the recesses comprises a sidewall having an edge inclined toward the gate structure; forming a source structure in one of the recesses; and forming a drain structure in another one of the recesses, an entirety of the source structure and an entirety of the drain structure being of complementary conductivity types with respect to one another and having different materials.

2 . The method of forming a tunneling transistor according to claim 1 , wherein the gate structure comprises a spacer and the edge is formed under the spacer in a projecting direction.

3 . The method of forming a tunneling transistor according to claim 1 , wherein the recesses are formed through a dry etching process.

4 . The method of forming a tunneling transistor according to claim 1 , wherein the source structure and the drain structure are asymmetric in shape.

5 . The method of forming a tunneling transistor according to claim 1 , further comprising:
performing an ion implanting process before the source structure and the drain structure are formed, to form a doped region on surfaces of the sidewall.

6 . The method of forming a tunneling transistor according to claim 1 , further comprising:
performing an in situ doping process while the source structure and the drain structure are formed.

7 . The method of forming a tunneling transistor according to claim 1 , wherein the forming of the recesses comprising:
forming a first recess at one side of the gate structure in the fin shaped structure; and forming a second recess at another side of the gate structure in the fin shaped structure, wherein the source structure is formed in the first recess before the second recess is formed.

8 . A tunneling transistor comprising:
a fin shaped structure disposed in a substrate; a source structure disposed in the fin shaped structure, wherein the source structure comprises a first material and a concentration of a first element within the first material is gradually decreased in a direction away from a channel region; a drain structure disposed in the fin shaped structure, an entirety of the source structure and an entirety of the drain structure being of complementary conductivity types with respect to one another, wherein the drain structure comprises a second material and a concentration of a second element within the second material and different from the first element is gradually decreased in a the direction away from the channel region, wherein the second material is different from the first material and the second element is different from the second element; the channel region disposed in the fin shaped structure between the source structure and the drain structure, and a sidewall of the source structure and a sidewall of the drain structure being inclined toward the channel region; a gate structure disposed on the channel region; and a hetero tunneling junction vertically disposed between the channel region and the source structure, and between the channel region and the drain structure in the fin shaped structure.

9 . The tunneling transistor according to claim 8 , wherein the source structure and the drain structure comprise an asymmetric shape.

10 . The tunneling transistor according to claim 8 , wherein the source structure and the drain structure are respectively disposed in two recesses and each of the recesses comprises a sidewall having an edge inclined toward the gate structure.

11 . The tunneling transistor according to claim 10 , further comprising a doped region disposed on surfaces of the sidewall.

12 . The tunneling transistor according to claim 10 , wherein the gate structure comprises a spacer and the sidewall of the source structure or the drain structure is disposed under the spacer in a projecting direction.

13 . The tunneling transistor according to claim 8 , wherein an opposite sidewall opposite to the sidewall of the source structure, or an opposite sidewall opposite to the sidewall of the drain structure also has an inclined edge is vertical to the substrate.

14 . The tunneling transistor according to claim 8 , wherein an opposite sidewall opposite to the sidewall of the source structure, or an opposite sidewalls opposite to the sidewall of the drain structure also has an inclined edge.

15 . The tunneling transistor according to claim 8 , wherein the first material comprises SiGe and the second material comprises SiP or SiC.

16 . The tunneling transistor according to claim 15 , wherein the first element comprises Ge and the second element comprises P or C.

17 . The tunneling transistor according to claim 8 , wherein the source structure or the drain structure comprises SiP.

18 . The tunneling transistor according to claim 10 , wherein the first material comprises SiP or SiC and the second material comprises SiGe, and the first element comprises C or P and the second element comprises Ge.

Assignees

• United Microelectronics Corp

Inventors

• Chen Cheng-Guo
• Wu Kun-Yuan
• Chen Tai-You
• Ho Chiu-Sheng
• Yang Po-Kang
• Lo Ta-Kang

Classifications

• H01L29/7848

  Electricity · mapped topic

• H01L29/0847

  Electricity · mapped topic

• H01L29/7851 Primary

  Electricity · mapped topic

• H01L29/165

  Electricity · mapped topic

• H01L29/66636

  Electricity · mapped topic