Semiconductor device and finfet transistor

Patent metadata

Field	Value
Publication number	US-2018006063-A1
Application number	US-201715707250-A
Country	US
Kind code	A1
Filing date	Sep 18, 2017
Priority date	Jun 1, 2015
Publication date	Jan 4, 2018
Grant date	—

Abstract

The present disclosure provides semiconductor devices, fin field-effect transistors and fabrication methods thereof. An exemplary fin field-effect transistor includes a semiconductor substrate; an insulation layer configured for inhibiting a short channel effect and increasing a heat dissipation efficiency of the fin field-effect transistor formed over the semiconductor substrate; at least one fin formed over the insulation layer; a gate structure crossing over at least one fin and covering top and side surfaces of the fin formed over the semiconductor substrate; and a source formed in the fin at one side of the gate structure and a drain formed in the fin at the other side of the gate structure.

First claim

1 - 14 . (canceled)

15 . A semiconductor device, comprising:
a semiconductor substrate; a plurality of fins over the semiconductor substrate; and an insulation layer, including a first insulation layer and a second insulation layer, wherein the first insulation layer has a first portion under a lower portion of each fin and a second portion in the substrate between adjacent fins, and the second insulation layer is on the first insulation layer between adjacent fins.

16 . The semiconductor device according to claim 15 , wherein:
the insulation layer is made of nitrogen-doped silicon oxide.

17 . The semiconductor device according to claim 15 , wherein:
a thickness of the insulation layer is in a range of approximately 2 Å-200 Å.

18 . A fin field-effect transistor, comprising:
a semiconductor substrate; a plurality of fins over the semiconductor substrate; an insulation layer, including a first insulation layer and a second insulation layer, wherein the first insulation layer has a first portion under a lower portion of each fin and a second portion in the substrate between adjacent fins, and the second insulation layer is on the first insulation layer between adjacent fins; a gate structure crossing over at least one fin and covering top and side surfaces of the fin formed over the semiconductor substrate; and a source formed in the first fin at one side of the gate structure and a drain formed in the fin at the other side of the gate structure.

19 . The fin field-effect transistor according to claim 18 , wherein:
the insulation layer is made of nitrogen-doped silicon oxide.

20 . The fin field-effect transistor according to claim 18 , wherein:
a thickness of the insulation layer is in a range of approximately 2 Å-200 Å.

21 . The semiconductor device according to claim 15 , wherein:
the insulation layer is configured for inhibiting a short channel effect and increasing a heat dissipation efficiency of a semiconductor device formed over the semiconductor substrate.

22 . The semiconductor device according to claim 15 , wherein:
the first portion of the first insulation layer is above the semiconductor substrate; and the second portion of the first insulation layer is extended into the semiconductor substrate.

23 . The fin field-effect transistor according to claim 18 , wherein:
the insulation layer is configured for inhibiting a short channel effect and increasing a heat dissipation efficiency of the fin field-effect transistor formed over the semiconductor substrate.

24 . The fin field-effect transistor according to claim 18 , wherein:
the first portion of the first insulation layer is above the semiconductor substrate; and the second portion of the first insulation layer is extended into the semiconductor substrate.

Assignees

• Semiconductor Mfg International (Shanghai) Corporation

Inventors

• Xie Xinyun
• Zhou Ming

Classifications

• H10W10/181

  Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers · CPC title

• H10P90/1906

  Preparing SOI wafers · CPC title

• H10P50/695

  characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask · CPC title

• H10P50/642

  Chemical etching · CPC title

• H10P50/242 Primary

  of Group IV materials · CPC title