Integrated circuit and method for processing synchronized network frames using a hardware synchronization circuit

Patent metadata

Field	Value
Publication number	US-2017366331-A1
Application number	US-201615187490-A
Country	US
Kind code	A1
Filing date	Jun 20, 2016
Priority date	Jun 20, 2016
Publication date	Dec 21, 2017
Grant date	—

Abstract

In an embodiment, an integrated circuit (IC) device is disclosed. In the embodiment, the IC device includes an Ethernet frame processor, at least one Ethernet port coupled to the Ethernet frame processor, and a hardware synchronization circuit coupled to the Ethernet frame processor and to the at least one Ethernet port, the hardware synchronization circuit including a controller, a local clock, a media-independent peripheral coupled to the controller, and a media-dependent peripheral coupled to the media-independent peripheral, wherein power can be provided to the hardware synchronization circuit independent of the Ethernet frame processor.

First claim

What is claimed is:

1 . An integrated circuit (IC) device, the IC device comprising:
an Ethernet frame processor; at least one Ethernet port coupled to the Ethernet frame processor; and a hardware synchronization circuit coupled to the Ethernet frame processor and to the at least one Ethernet port, the hardware synchronization circuit comprising:
a controller;
a local clock coupled to the controller;
a media-independent peripheral coupled to the controller; and
a media-dependent peripheral coupled to the media-independent peripheral;
wherein power can be provided to the hardware synchronization circuit independent of the Ethernet frame processor.

2 . The IC device of claim 1 , wherein the hardware synchronization circuit is configured to perform IEEE 802.1AS functions while the Ethernet frame processor is powered down.

3 . The IC device of claim 2 , wherein a double-type integer used in IEEE 802.1AS functions is stored in a 64-bit register with the first 4 bits allocated to an integer value and the trailing 60 bits allocated to a fractional value.

4 . The IC device of claim 2 , wherein timestamp values are stored using std_logic_vectors.

5 . The IC device of claim 2 , wherein rate ratio is calculated using a non-restoring division algorithm implemented via iterative subtraction and shifting using registers in the hardware synchronization circuit.

6 . The IC device of claim 2 , wherein residence time and propagation delay are calculated using subtraction and shift registers in the hardware synchronization circuit.

7 . The IC device of claim 2 , wherein a local synchronization clock is configured using separate adders and subtractors to detect and compute seconds and nanoseconds separately.

8 . The IC device of claim 2 , wherein the hardware synchronization circuit is configured to process a partial range of header data in an Ethernet frame and store the data in registers in the hardware synchronization circuit.

9 . The IC device of claim 1 , wherein the media-dependent peripheral is coupled to a single port.

10 . The IC device of claim 1 , wherein the controller is configured to forward a frame to at least one of a microcontroller coupled to the IC device and the Ethernet frame processor when the frame includes an IEEE 802.1AS function that the hardware synchronization circuit cannot process.

11 . A method for processing synchronized network frames, the method comprising:
powering up a hardware synchronization circuit; receiving an IEEE 802.1AS frame; determining if the IEEE 802.1AS frame requires processing by a microcontroller; powering up the microcontroller, processing the IEEE 802.1AS frame using the microcontroller if the IEEE 802.1AS frame requires processing by a microcontroller, and powering down the microcontroller; and processing the IEEE 802.1AS frame using a hardware synchronization circuit if the IEEE 802.1AS frame does not require processing by a microcontroller.

12 . The method of claim 11 , wherein a double-type integer used in processing the IEEE 802.1AS frame is stored in a 64-bit register in the hardware synchronization circuit with the first 4 bits allocated to an integer value and the trailing 60 bits allocated to a fractional value.

13 . The method of claim 11 , wherein timestamp values are stored using std_logic_vectors.

14 . The method of claim 11 , wherein rate ratio is calculated using a non-restoring division algorithm implemented via iterative subtraction and shifting using registers in the hardware synchronization circuit.

15 . The method of claim 11 , wherein residence time and propagation delay are calculated using subtraction and shift registers in the hardware synchronization circuit.

16 . The method of claim 11 , wherein a local synchronization clock is configured using separate adders and subtractors to detect and compute seconds and nanoseconds separately.

17 . The method of claim 11 , wherein the hardware synchronization circuit is configured to process a partial range of header data in an Ethernet frame and store the data in registers in the hardware synchronization circuit.

18 . The method of claim 11 , wherein the controller is configured to forward a frame to at least one of a microcontroller coupled to the IC device and the Ethernet frame processor when the frame includes an IEEE 802.1AS function that the hardware synchronization circuit cannot process.

19 . An automobile Ethernet network, the network comprising:
at least one switch, the switch configured with a hardware synchronization circuit and coupled to a microcontroller; at least one end node, the end node coupled to the switch, a microcontroller, and a transceiver within which a hardware synchronization circuit is configured; and a time-sensitive Ethernet device coupled to the microcontroller that is coupled to the end node; wherein the network is synchronized using IEEE 802.1AS; and wherein IEEE 802.1AS functions are performed by the hardware synchronization circuit in the switch and in the transceiver within the end node while the microcontrollers coupled to the switch and end node remain powered off.

20 . The automobile Ethernet network of claim 19 , wherein resynchronization of the powered off microcontrollers coupled to the at least one switch can be facilitated by the hardware synchronization circuit in the at least one switch and resynchronization of the powered off microcontrollers coupled to the at least one end node can be facilitated by the hardware synchronization circuit in the at least one end node.

Assignees

• Nxp Bv

Inventors

• Vermeulen Hubertus Gerardus Hendrikus
• Concer Nicola

Classifications

• H04J3/0644 Primary

  External master-clock · CPC title

• H04J3/0655

  using timestamps · CPC title

• H04L7/0008 Primary

  Synchronisation information channels, e.g. clock distribution lines · CPC title

• H04L69/22

  Parsing or analysis of headers · CPC title

• H04J3/0682

  by delay compensation, e.g. by compensation of propagation delay or variations thereof, by ranging · CPC title