Integrated circuit and method for processing synchronized network frames using a hardware synchronization circuit
US-10530560-B2 · Jan 7, 2020 · US
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Patent family 59053888
This patent family groups 2 related publications across US. Members often share priority claims or equivalent filings in different countries.
| Field | Value |
|---|---|
| Family ID | 59053888 |
| Family type | — |
| Earliest priority | Jun 20, 2016 |
| First filing country | US |
| Member publications | 2 |
| Countries | US |
| Representative publication | US10530560B2 — Integrated circuit and method for processing synchronized network frames using a hardware synchronization circuit |
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US10530560B2 — Integrated circuit and method for processing synchronized network frames using a hardware synchronization circuit (published Jan 7, 2020)
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