Nonvolatile memory cross-bar array

Patent metadata

Field	Value
Publication number	US-2017358352-A1
Application number	US-201415535765-A
Country	US
Kind code	A1
Filing date	Dec 15, 2014
Priority date	Dec 15, 2014
Publication date	Dec 14, 2017
Grant date	—

Abstract

Provided in one example is a nonvolatile memory cross-bar array. The array includes: a number of junctions formed by a number of row lines intersecting a number of column lines; a first set of controls at a first set of the junctions coupling between a first set of the row lines and a first set of the column lines; a second set of controls at a second set of the junctions coupling between a second set of the row lines and a second set of the column lines; and a current collection line to collect currents from the controls of the first set and the second set through their respective column lines and output a result current corresponding to a sum of a first dot product and a second dot product.

First claim

What is claimed:

1 . A nonvolatile memory cross-bar array, including:
a number of junctions formed by a number of row lines intersecting a number of column lines; a first set of controls at a first set of the junctions coupling between a first set of the row lines and a first set of the column lines, each control of the first set including a first transistor and a first resistive memory element; a second set of controls at a second set of the junctions coupling between a second set of the row lines and a second set of the column lines, each control of the second set including a second transistor and a second resistive memory element, wherein each column line includes a junction of the first set and a junction of the second set in two different row lines; and a current collection line to collect currents from the controls of the first set and the second set through their respective column lines and output a result current corresponding to a sum of a first dot product and a second dot product corresponding respectively to currents collected from the controls of the first set and the second set.

2 . The nonvolatile memory cross-bar array of claim 1 ,
wherein the first set of controls and the second set of controls are independently to;
receive a number of programming signals at the respective controls, the programming signals defining a number of matrix values; and
receive a number of vector signals at the respective controls, the vector signals defining a number of vector values to be applied to the respective controls; and
wherein the nonvolatile memory cross-bar array is to calculate the first dot product and the second dot product of the respective matrix values and vector values using the currents collected respectively from the controls of the first set and the second set.

3 . The nonvolatile memory cross-bar array of claim 1 , wherein the first resistive memory element and the second resistive memory element have different preset conductance values.

4 . The nonvolatile memory cross-bar array of claim 1 , wherein one or both of the first resistive memory element and the second resistive memory element is a resistive random-access memory.

5 . The nonvolatile memory cross-bar array of claim 1 , wherein one or both of the first resistive memory element and the second resistive memory element is a memristor.

6 . The nonvolatile memory cross-bar array of claim 1 , wherein calculations involving respective sums and products of the first dot product and second dot product are performed simultaneously by the nonvolatile memory cross-bar array.

7 . The nonvolatile memory cross-bar array of claim 1 , further including a third set of controls at a third set of the junctions, coupling between a third set of the row lines and a third set of the column lines, each control of the third set including a third transistor and a third resistive memory element and each column line includes junctions of the first set, the second set, and the third set in three different row lines;
wherein the sum is further calculated to include a third dot product using currents collected from the controls of third set, corresponding to the respective matrix values and vector values of the third set.

8 . A system, including:
a processor; and a nonvolatile memory cross-bar array coupled to the processor, the memristor cross-bar array including:
a number of junctions formed by a number of row lines intersecting a number of column lines;
a first set of controls at a first set of the junctions coupling between a first set of the row lines and a first set of the column lines, each control of the first set including a first transistor and a first resistive memory element; and
a second set of controls at a second set of the junctions coupling between a second set of the row lines and a second set of the column lines, each control of the second set including a second transistor and a second resistive memory element, wherein each column line includes a junction of the first set and a junction of the second set in two different row lines;
wherein the first set of controls and the second set of controls are independently to:
receive a number of programming signals at the respective controls, the programming signals defining a number of matrix values; and
receive a number of vector signals at the respective controls, the vector signals defining a number of vector values to be applied to the respective controls; and
wherein a sum of a first dot product and a second dot product is calculated using currents collected from respectively the controls of the first set and the second set, corresponding to the respective matrix values and vector values.

9 . The system of claim 8 , further including a current collection line to collect currents from the controls of the first set and the second set through their respective column lines and output a result current corresponding to the sum of the first dot product and the second dot product.

10 . The system of claim 8 , wherein the calculation of the sum does not involve storing the matrix values and vector values in a storing memory circuit in the system.

11 . The system of claim 8 , wherein one or both of the first resistive memory element and the second resistive memory element is a resistive random-access memory.

12 . The system of claim 8 , wherein the first resistive memory element and the second resistive memory element have different preset conductance values.

13 . A method of calculating, including:
applying a first set of voltages to a first set of row lines within a nonvolatile memory cross-bar array to change resistive values of a corresponding first set of controls located at a first set of junctions between the first set of row lines and a first set of column lines, the first set of voltages defining a corresponding number of values within a first matrix, and each control of the first set including a first transistor and a first resistive memory element; applying a second set of voltages to a second set of row lines within the nonvolatile memory cross-bar array to change resistive values of a corresponding second set of controls located at a second set of junctions between the second set of row lines and a second set of column lines, the second voltages defining a corresponding number of values within a second matrix, and each control of the second set including a second transistor and a second resistive memory element, wherein each column line includes a junction of the first set and a junction of the second set in two different row lines; applying a third set and a fourth set of voltages respectively to the row lines of the first set and second set, the voltages of the third set and fourth set defining a corresponding number of vector values applied to the first matrix and the second matrix, respectively; collecting currents through the respective column lines of the controls of the first set and the second set corresponding to the respective matrix values and vector values of the first and second matrices; and calculating a sum of a first dot product and a second dot product using the currents collected respectively from the controls of the first set and the second set, corresponding to the respective matrix values and vector values.

14 . The method of claim 13 , further including controlling the controls of the first set and the second set using machine-readable instructions to calculate independently the first dot product and the second dot product.

15 . The method of claim 13 , wherein calculating the sum of the first dot product and the second dot produc

Assignees

• Hewlett Packard Entpr Dev Lp

Inventors

• Ge Ning
• Yang Jianhua
• Strachan John Paul
• Hu Miao

Classifications

• G06G7/16

  for multiplication or division {(G06G7/19 and G06G7/24 take precedence; measuring electric power G01R21/00)} · CPC title

• G11C13/0007 Primary

  comprising metal oxide memory material, e.g. perovskites · CPC title

• G11C13/004 Primary

  Reading or sensing circuits or methods · CPC title

• G11C2213/79

  Array wherein the access device being a transistor · CPC title

• G11C2013/0057

  Read done in two steps, e.g. wherein the cell is read twice and one of the two read values serving as a reference value · CPC title