Bottom pinned SOT-MRAM bit structure and method of fabrication

Patent metadata

Field	Value
Publication number	US-9768229-B2
Application number	US-201514920853-A
Country	US
Kind code	B2
Filing date	Oct 22, 2015
Priority date	Oct 22, 2015
Publication date	Sep 19, 2017
Grant date	Sep 19, 2017

Abstract

Embodiments of the present disclosure generally relate to data storage and computer memory systems, and more particularly, to a SOT-MRAM chip architecture. The SOT-MRAM chip architecture includes a plurality of leads, a plurality of memory cells, and a plurality of transistors. The leads may be made of a material having large spin-orbit coupling strength and high electrical resistivity. Each lead of the plurality of leads may include a plurality of first portions and a plurality of second portions distinct from the first portions. The electrical resistivity of the second portions is less than that of the first portions, so the total electrical resistivity of the lead is reduced, leading to improved power efficiency and signal to noise ratio.

First claim

What is claimed is:

1. A magnetoresistive random access memory (MRAM) device, comprising:
two or more leads, wherein at least one lead comprises a first portion and a second portion, the first portion having a first width that is different from a second width of the second portion;
a memory cell coupled to each lead; and
a transistor coupled to the memory cell.

2. The device of claim 1 , wherein the memory cell comprises a reference layer, a barrier layer, and a free layer.

3. The device of claim 2 , wherein the free layer is in contact with the lead, and wherein a writing process is performed by a half-select mechanism that includes a combination of flowing a current along a lead of the two or more leads and applying a voltage to the memory cell.

4. The device of claim 2 , further comprising a spin-orbit torque layer disposed between the free layer of the memory cell and the lead.

5. A magnetoresistive random access memory ( MRAM) device, comprising:
a lead comprising a first portion and a second portion distinct from the first portion, wherein the first portion has a first width and the second portion has a second width, and wherein the first width is smaller than the second width;
a memory cell coupled to the first portion of the lead; and
a of transistor coupled to the memory cell.

6. The device of claim 5 , wherein the memory cell comprises a reference layer, a barrier layer, and a free layer.

7. The device of claim 6 , wherein the free layer is in contact with the first portion, and wherein a writing process is performed by a half-select mechanism that includes a combination of flowing a current along the lead and applying a voltage to the memory cell.

8. The device of claim 6 , further comprising a spin-orbit torque layer disposed between the free layer of the memory cell and the first portion.

9. The device of claim 5 , wherein the lead is made of a material selected from the group consisting of Pt, Ta, W, Hf, Ir, CuBi, CuIr, and AuW.

10. The device of claim 5 , wherein the first portion is in contact with the memory cell and the second portion is spaced from the memory cell.

11. The device of claim 5 , wherein the first width ranges from about 10 nm to about 500 nm and the second width ranges from about 10 nm to about 500 nm.

12. A magnetoresistive random access memory( MRAM) device, comprising:
a lead comprising a first portion and a second portion distinct from the first portion, wherein the first portion is made of a first material and the second portion is made of a second material, and wherein the first material is different from the second material;
a memory cell coupled to the first portion of the lead; and a transistor couple to the memory cell.

13. The device of claim 12 , wherein the memory cell comprises a reference layer, a barrier layer, and a free layer.

14. The device of claim 13 , wherein the first portion is in contact with the free layer of the memory cell and the second portion is spaced from the memory cell, and wherein a writing process is performed by a half-select mechanism that includes a combination of flowing a current along the lead and applying a voltage to the memory cell.

15. The device of claim 13 , wherein the memory cell further comprises a spin-orbit torque layer disposed on the free layer, wherein the first portion is in contact with the spin-orbit torque layer of the memory cell and the second portion is spaced from the memory cell.

16. The device of claim 12 , wherein the first material is selected from the group consisting of Pt, Ta, W, Hf, Ir, CuBi, CuIr, and AuW.

17. The device of claim 16 , wherein the second material comprises one or more of copper, aluminum, and a material selected from the group consisting of Pt, Ta, W, Hf, Ir, CuBi, CuIr, and AuW that is doped with a dopant.

18. The device of claim 16 , wherein the second material comprises one or more layers including at least one layer comprising one or more of copper, aluminum, and a material selected from the group consisting of Pt, Ta, W, Hf, Ir, CuBi, CuIr, and AuW that is doped with a dopant.

19. The device of claim 18 , wherein the one or more layers include a first layer comprising one or more of copper and aluminum, and a second layer comprising a material selected from the group consisting of Pt, Ta, W, Hf, Ir, CuBi, CuIr, and AuW.

20. The device of claim 12 , wherein the first portion has a first width and the second portion has a second width, and wherein the first width is smaller than the second width.

21. The device of claim 12 , wherein the second material comprises the first material with a dopant.

22. The device of claim 21 , wherein the first material is tantalum and the second material is tantalum doped with nitrogen.

Assignees

• Western Digital Tech Inc

Inventors

• Braganca Patrick M
• Tseng Hsin-Wei
• Wan Lei

Classifications

• G11C11/1675

  Writing or programming circuits or methods · CPC title

• G11C11/161 Primary

  details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell · CPC title

• G11C11/18

  using Hall-effect devices · CPC title

• H01L27/228 Primary

  Electricity · mapped topic

• H01L43/02

  Electricity · mapped topic