Semiconductor Packaging Structure and Process

Patent metadata

Field	Value
Publication number	US-2017345708-A1
Application number	US-201715676326-A
Country	US
Kind code	A1
Filing date	Aug 14, 2017
Priority date	Dec 20, 2013
Publication date	Nov 30, 2017
Grant date	—

Abstract

A method and structure for packaging a semiconductor device are provided. In an embodiment a first substrate is bonded to a second substrate, which is bonded to a third substrate. A thermal interface material is placed on the second substrate prior to application of an underfill material. A ring can be placed on the thermal interface material, and an underfill material is dispensed between the second substrate and the third substrate. By placing the thermal interface material and ring prior to the underfill material, the underfill material cannot interfere with the interface between the thermal interface material and the second substrate, and the thermal interface material and ring can act as a physical barrier to the underfill material, thereby preventing overflow.

First claim

What is claimed is:

1 . A semiconductor device comprising:
a first substrate with a first surface; a second substrate bonded to the first surface; a first thermal interface material located on the first surface laterally separated from the second substrate; and an underfill material located between the first substrate and the second substrate, the underfill material extending in a first direction from a first point to physically contact the first thermal interface material, the first point being between the first substrate and the second substrate, and the underfill material extending in a second direction from the first point only partially towards the first thermal interface material.

2 . The semiconductor device of claim 1 , further comprising a third substrate bonded to the first substrate.

3 . The semiconductor device of claim 2 , wherein the third substrate is a printed circuit board.

4 . The semiconductor device of claim 1 , wherein the first substrate is a logic die.

5 . The semiconductor device of claim 4 , wherein the first substrate further comprises through substrate vias.

6 . The semiconductor device of claim 4 , wherein the second substrate is a memory die.

7 . The semiconductor device of claim 4 , further comprising a third substrate interconnected to the second substrate.

8 . A semiconductor device comprising:
a first substrate; a second substrate, wherein the first substrate is bonded to a first side of the second substrate; a structure comprising:
a first thermal interface material on the second substrate; and
a first exposed surface facing away from the first side, the first exposed surface being located a first distance away from the first side and wherein the first substrate has a second surface facing away from the first side, the second surface being located a second distance away from the first side, the second distance being greater than the first distance; and
an underfill material between the first substrate and the second substrate, wherein the underfill material has a third surface facing away from the second substrate that is in contact with both the first thermal interface material and a sidewall of the first substrate perpendicular to the second substrate, the third surface being closer to second substrate than the second surface.

9 . The semiconductor device of claim 8 , wherein the first thermal interface material comprises a silicone compound.

10 . The semiconductor device of claim 8 , wherein the first thermal interface material comprises a metal-based thermal paste.

11 . The semiconductor device of claim 8 , wherein the first thermal interface material comprises a solid metal.

12 . The semiconductor device of claim 8 , wherein the first thermal interface material has a thickness of between about 5 μm and about 500 μm.

13 . The semiconductor device of claim 8 , wherein the first thermal interface material is separated from the first substrate by a distance of between about 0.1 mm and about 20 mm.

14 . The semiconductor device of claim 8 , wherein the structure further comprises a ring located on the first thermal interface material.

15 . A semiconductor device comprising:
a first thermal interface material on a first side of a first substrate, wherein a second substrate is bonded to the first side of the first substrate; a first ring on the first thermal interface material, wherein the second substrate extends further from the first substrate than the first ring; an underfill material between the first substrate and the second substrate, wherein the underfill material extends in a first direction from a first point to physically contact the first thermal interface material, the first point being between the first substrate and the second substrate, and wherein the underfill material extends in a second direction from the first point only partially towards the first thermal interface material; and a lid over the first substrate and the second substrate, the lid being in thermal connection with the first ring.

16 . The semiconductor device of claim 15 , further comprising a second ring on the first thermal interface material.

17 . The semiconductor device of claim 15 , wherein the first ring has a thickness of between about 0.05 m and about 5 mm.

18 . The semiconductor device of claim 15 , wherein the first ring encircles the second substrate.

19 . The semiconductor device of claim 15 , further comprising a third substrate bonded to the first substrate.

20 . The semiconductor device of claim 19 , further comprising a second underfill material located between the first substrate and the third substrate.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Ho Kuan-Lin
• Chen Chin-Liang
• Lin Wei-Ting
• Liu Yu-Chih
• Lin Shih-Yen

Classifications

• H10W76/63

  characterised by their shape or disposition, e.g. between cap and walls of a container · CPC title

• H10W76/60

  Seals · CPC title

• H10W90/288

  characterised by arrangements for thermal management of the stacked chips · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W72/072

  of bump connectors · CPC title