Secure system on chip

Patent metadata

Field	Value
Publication number	US-2017344261-A1
Application number	US-201615167269-A
Country	US
Kind code	A1
Filing date	May 27, 2016
Priority date	May 27, 2016
Publication date	Nov 30, 2017
Grant date	—

Abstract

A secure SoC IC is disclosed herein. In embodiments, a SoC IC for computing may comprise a plurality of processor cores, wherein each processor core has at least one level of private cache and its own private memory to securely execute one or more applications. Further, the SoC IC may include a plurality of isochronous memory disposed between selected pairs of the processor cores to provide deterministic data transfers between the processor core pairs. Other embodiments may be disclosed or claimed.

First claim

What is claimed is:

1 . A system on chip (SOC) integrated circuit (IC) for computing, comprising:
a first, second, third and fourth processor cores, wherein each processor core has at least one level of private cache and its own private memory to securely execute one or more applications; a first, a second, and a third isochronous memory disposed between and respectively coupling the first, the second and the third processor core to the fourth processor core, to provide deterministic data transfers between the first, the second and the third processor core, and the fourth processor core.

2 . The SOC IC of claim 1 , further comprising a direct memory access (DMA) device, and another isochronous memory disposed between and coupling the DMA device and the fourth processor core; wherein the another isochronous memory provides the DMA device with deterministic accesses to the private memory of the fourth processor core.

3 . The SOC IC of claim 1 , further comprising an Ethernet, wireless, serial or parallel input/output (I/O) interface coupled to the fourth processor core, wherein all inputs into or outputs from the SOC IC are routed through the Ethernet, wireless, serial or parallel I/O interface and the fourth processor core.

4 . The SOC IC of claim 1 , wherein the first, second, and third processor cores respectively host applications of a first, a second, and a third network of first, second and third different security levels.

5 . A system on chip (SOC) integrated circuit (IC) for computing, comprising:
a plurality of processor cores, wherein each processor core has at least one level of private cache and its own private memory to securely execute one or more applications; and a plurality of isochronous memory disposed between selected pairs of the processor cores to provide deterministic data transfers between the processor core pairs.

6 . The SOC IC of claim 5 , wherein the at least one level of private cache of each processor core is physically indexed, or selectively lockable.

7 . The SOC IC of claim 5 , wherein each processor core has at least two levels of private cache; wherein the level 2 cache of each processor core is partitioned into at least a code section and a data section.

8 . The SOC IC of claim 5 , wherein the level 2 cache of each processor core is flash invalidated, when the level cache 2 cache of each processor core needs to be invalidated.

9 . The SOC IC of claim 5 , where each processor core further comprises a plurality of programmable registers that are lockable.

10 . The SOC IC of claim 9 , wherein each processor core further comprises an error correcting codeword (ECC) engine coupled to the lockable registers, the at least one level private cache or private memory of the processor core to perform ECC service for data stored in the lockable registers, the at least one level private cache or private memory of the processor core.

11 . The SOC IC of claim 5 , further comprising global shared memory and a plurality of redundant isochronous bus coupling the plurality of processor cores and the global shared memory; wherein the redundant isochronous buses are to provide deterministic accesses to the global shared memory by the plurality of processor cores.

12 . The SOC IC of claim 5 , further comprising a direct memory access (DMA) device, and another isochronous memory disposed between and coupling the DMA device and one of the plurality of processor cores; wherein the another isochronous memory provides the DMA device with deterministic accesses to the private memory of the one processor core.

13 . The SOC IC of claim 5 , further comprising an Ethernet, wireless, serial or parallel input/output (I/O) interface coupled to one of the plurality of processor cores, wherein all inputs into or outputs from the SOC IC are routed through the Ethernet, wireless, serial or parallel I/O interface and the one processor core.

14 . The SOC IC of claim 5 , further comprising a system monitor core to perform system management services for the SOC IC; wherein the system monitor core is coupled to and has access to all private memory and selected registers of the processor cores.

15 . The SOC IC of claim 14 , wherein the system management services include one or more of time validation of software, validation of a boot sequence, or monitor of the processor cores.

16 . The SOC IC of claim 5 , further comprising a global clock which clock time is available to all processor cores for synchronization; and wherein the global clock can be synchronized with a clock time external to the SOC IC.

17 . The SOC IC of claim 5 , wherein a first and a second of the processor cores respectively host applications of a first and a second network of first and second different security levels.

18 . An apparatus for computing, comprising:
a system on chip (SOC) integrated circuit (IC) having
a plurality of processor cores, wherein each processor core has at least one level of private cache and its own private memory to securely execute one or more applications; and
a plurality of isochronous memory disposed between selected pairs of the processor cores to provide deterministic data transfers between the processor core pairs; and
a display.

19 . The apparatus of claim 18 , wherein the display is a touch-sensitive display.

20 . The apparatus of claim 18 , further comprising a camera.

21 . The apparatus of claim 18 , further comprising one or more sensors.

22 . The apparatus of claim 18 , wherein the apparatus is a selected one of a wearable computing device, a smartphone, a computing tablet or a laptop computer.

23 . The apparatus of claim 18 , wherein a first and a second of the processor cores of the SOC IC respectively host applications of a first and a second network of first and second different security levels.

Assignees

• Wind River Systems Inc

Inventors

• Sauks Mati

Classifications

• G06F13/4068

  Electrical coupling · CPC title

• G06F3/0653

  Monitoring storage devices or systems · CPC title

• G06F12/0897

  with two or more cache hierarchy levels (with multilevel cache hierarchies G06F12/0811) · CPC title

• G06F11/1064

  in cache or content addressable memories · CPC title

• G06F3/0683

  Plurality of storage devices · CPC title