Semiconductor device and method for manufacturing the same

Patent metadata

Field	Value
Publication number	US-2017309589-A1
Application number	US-201715423473-A
Country	US
Kind code	A1
Filing date	Feb 2, 2017
Priority date	Apr 21, 2016
Publication date	Oct 26, 2017
Grant date	—

Abstract

Provided are a semiconductor device and a method for manufacturing the same. The semiconductor device according to an embodiment of the inventive concept includes a first semiconductor chip having a recess portion in one surface thereof; a first adhesion pattern filled within the recess portion of the first semiconductor chip; and a second semiconductor chip disposed on the first adhesion pattern. The second semiconductor chip may represent improved heat dissipation characteristics.

First claim

What is claimed is:

1 . A semiconductor device comprising:
a first semiconductor chip having a recess portion in one surface thereof; a first adhesion pattern filled within the recess portion of the first semiconductor chip; and a second semiconductor chip attached to the first semiconductor chip by the first adhesion pattern, wherein the first adhesion pattern is disposed between the first semiconductor chip and the second semiconductor chip.

2 . The semiconductor device of claim 1 , wherein the second semiconductor chip physically contacts the first adhesion pattern and the first semiconductor chip.

3 . The semiconductor device of claim 1 , wherein the first semiconductor chip has a thermal conductivity greater than that of the first adhesion pattern.

4 . The semiconductor device of claim 1 , wherein the first semiconductor chip further comprises a metal pattern,
wherein the recess portion is disposed within the metal pattern.

5 . The semiconductor device of claim 4 , wherein the second semiconductor chip physically contacts the metal pattern and the first adhesion pattern.

6 . The semiconductor device of claim 1 , further comprising a metal layer interposed between the first adhesion pattern and the second semiconductor chip,
wherein the metal layer has a thermal conductivity greater than that of the first adhesion pattern.

7 . The semiconductor device of claim 1 , further comprising a second adhesion pattern disposed on the one surface of the first semiconductor chip and a side surface of the second semiconductor chip,
wherein the second adhesion pattern comprises the same material as the first adhesion pattern.

8 . The semiconductor device of claim 1 , wherein the recess portion has a height of about 100 nm to about 10 μm.

9 . The semiconductor device of claim 1 , further comprising a substrate,
wherein the first semiconductor chip is disposed on the substrate.

10 . A method for manufacturing a semiconductor device, the method comprising:
preparing a first semiconductor chip having a recess portion in one surface thereof; forming an adhesion pattern within the recess portion; and disposing a second semiconductor chip on the first semiconductor chip and the adhesion pattern.

11 . The method of claim 10 , wherein the second semiconductor chip contacts the adhesion pattern and the first semiconductor chip, and
the first semiconductor chip has a thermal conductivity greater than that of the adhesion pattern.

12 . The method of claim 10 , wherein the preparing of the first semiconductor chip comprises:
forming a mask pattern on the one surface of the first semiconductor chip; and etching the first semiconductor chip exposed by the mask pattern to form the recess portion.

13 . The method of claim 10 , wherein the forming of the adhesion pattern comprises applying the adhesion pattern on the first semiconductor chip to cover the one surface of the first semiconductor chip.

14 . The method of claim 13 , further comprising applying a pressure to the second semiconductor chip to allow a bottom surface of the second semiconductor chip to physically contact the one surface of the first semiconductor chip after the disposing the second semiconductor chip.

15 . The method of claim 10 , further comprising disposing the first semiconductor chip on a substrate.

Assignees

• Electronics & Telecommunications Res Inst

Inventors

• Kwack Myungjoon
• Kim Gyungock
• Park Jaegyu
• Oh Jin Hyuk
• Joo Jiho

Classifications

• H10W90/288 Primary

  characterised by arrangements for thermal management of the stacked chips · CPC title

• H10W90/271

  the chips having passive surfaces facing each other, i.e. in a back-to-back arrangement · CPC title

• H10W72/884

  Die-attach connectors and bond wires · CPC title

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/877

  Bump connectors and die-attach connectors · CPC title