Test structures for measuring silicon thickness in fully depleted silicon-on-insulator technologies

Patent metadata

Field	Value
Publication number	US-2017309524-A1
Application number	US-201715611576-A
Country	US
Kind code	A1
Filing date	Jun 1, 2017
Priority date	Aug 28, 2015
Publication date	Oct 26, 2017
Grant date	—

Abstract

Described are test structures and methods for measuring silicon thickness in fully depleted silicon-on-insulator technologies.

First claim

What is claimed is:

1 . An apparatus for determining a thickness of a fully depleted silicon-on-insulator layer disposed in a CMOS integrated circuit, the apparatus being disposed on a FDSOI substrate that also includes the CMOS integrated circuit, the apparatus comprising:
a test structure that includes at least one test circuit, the at least one test circuit including an isolated fully depleted silicon-on-insulator layer disposed above an isolated buried oxide layer and a gate dielectric disposed above the isolated fully depleted silicon-on-insulator layer and which further includes an Epi region surrounding the isolated fully depleted silicon-on-insulator layer to bias the isolated fully depleted silicon-on-insulator layer, the at least one test circuit providing:
a total capacitance measurement;
a gate dielectric capacitance measurement; and
a buried oxide capacitance measurement.

2 . The apparatus according to claim 1 , wherein the at least one test circuit includes a plurality of test circuits, wherein each of the plurality of test circuits include the isolated fully depleted silicon-on-insulator layer disposed above the isolated buried oxide layer, wherein a desired thickness of the isolated fully depleted silicon-on-insulator layer and a desired thickness of the isolated buried oxide layer on the plurality of test circuits is representative of, respectively, a thickness of the isolated fully depleted silicon-on-insulator layer and a thickness of the isolated buried oxide layer on the CMOS integrated circuit, the test structure further including:
a total capacitance measurement circuit as one of the plurality of test circuits and that provides a total capacitance measurement and includes a gate dielectric disposed above the isolated fully depleted silicon-on-insulator layer; a gate dielectric capacitance measurement circuit as another of the plurality of test circuits and that provides a gate dielectric capacitance measurement and includes a gate dielectric disposed above the isolated fully depleted silicon-on-insulator layer and which further includes an Epi region surrounding the isolated fully depleted silicon-on-insulator layer to bias the isolated fully depleted silicon-on-insulator layer in an inversion state; and a buried oxide capacitance measurement circuit as a further one of the plurality of test circuits that provides a buried oxide capacitance measurement.

3 . The apparatus according to claim 2 wherein the plurality of test circuits each further include a ground plane disposed between the buried oxide and one of an n-well and a p-well.

4 . The apparatus according to claim 2 wherein each of the plurality of test circuits are sized the same.

5 . The apparatus according to claim 2 wherein each of the plurality of test circuits are sized in a ratioed manner.

6 . The apparatus according to claim 2 , wherein the plurality of test circuits are each disposed in close proximity to each other on a scribe lane of the FDSOI substrate.

7 . The apparatus according to claim 2 , wherein the plurality of test circuits includes at least two sets of the plurality of test circuits disposed in disparate locations of the FDSOI substrate.

8 . The apparatus according to claim 7 , wherein the plurality of test circuits within each set of the plurality of test circuits are each disposed in close proximity to each other and within a single scribe lane of the FDSOI substrate.

9 . The apparatus according to claim 2 wherein the total capacitance measurement circuit has a first terminal connected to the gate dielectric and a second terminal connected to one of an n-well and a p-well, for obtaining the total capacitance measurement.

10 . The apparatus according to claim 2 wherein the gate dielectric capacitance measurement circuit has a first terminal connected to the gate dielectric and a second terminal connected to a source/drain regions disposed adjacent the isolated fully depleted silicon-on-insulator layer and a shield terminal connected to one of an n-well and p-well, for obtaining the gate dielectric capacitance measurement.

11 . The apparatus according to claim 2 wherein the buried oxide capacitance measurement circuit has a first terminal connected to a top the gate dielectric and a second terminal connected to one of an n-well and p-well, for obtaining the total capacitance measurement.

Assignees

• Pdf Solutions Inc

Inventors

• Saxena Sharad
• Brozek Thomas
• Yu Yuan
• Pak Mike Kyu Hyon
• Lunenborg Meindert Martin

Classifications

• H10P74/277

  Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers · CPC title

• H10P74/207

  Electrical properties, e.g. testing or measuring of resistance, deep levels or capacitance-voltage characteristics · CPC title

• G01R27/2605 Primary

  Measuring capacitance (capacitive sensors G01D5/24) · CPC title

• H01L22/12 Primary

  Electricity · mapped topic

• G01B7/08 Primary

  using capacitive means · CPC title