Wafer level system in package (sip) using a reconstituted wafer and method of making

Patent metadata

Field	Value
Publication number	US-2017301651-A1
Application number	US-201615144458-A
Country	US
Kind code	A1
Filing date	May 2, 2016
Priority date	Apr 18, 2016
Publication date	Oct 19, 2017
Grant date	—

Abstract

A package such as a system in package (SiP) includes a first die disposed in a first mold layer and coupled to a first dielectric layer disposed above the first mold and a second die disposed in a second mold layer and coupled to a second dielectric layer disposed above the second die. A pillar is disposed through the second mold layer and is coupled to a first metal layer disposed above the first dielectric layer. The first metal layer is coupled to the first die, and the pillar is coupled to a second metal layer disposed above the second dielectric layer.

First claim

1 . A package, comprising:
a first die disposed in a first mold layer and coupled to a first dielectric layer disposed above the first mold layer; a second die disposed in a second mold layer and coupled to a second dielectric layer disposed above the second die; and a third dielectric layer disposed above the second dielectric layer and comprising pins, solder balls, or solder bumps, wherein a pillar is disposed through the second mold layer and coupled to a first metal layer disposed above the first dielectric layer, the first metal layer being coupled to the first die, wherein the pillar is coupled to a second metal layer disposed above the second dielectric layer, the second metal layer being coupled to the second die and at least one of the solder balls, solder bumps or pins, and wherein the pillar is located between the first metal layer and the second metal layer.

2 . The package of claim 1 , further comprising:
a first via disposed through the first dielectric layer to a first pad disposed on the first die.

3 . The package of claim 1 , wherein the first die and the first mold layer are part of a reconstituted wafer.

4 . The package of claim 1 , wherein the first die, the first mold layer, the first dielectric layer, the second die, the second dielectric layer, and the second mold layer are part of a reconstituted wafer.

5 . The package of claim 1 , wherein the first die, the first mold layer, the first dielectric layer, the second die, and the second mold layer are part of a reconstituted wafer, wherein the second dielectric layer is above the second mold layer.

6 . The package of claim 5 , further comprising:
a third dielectric layer disposed below the second dielectric layer and above the second die, the third dielectric layer having an area, the area being the same as an area of the second die.

7 . The package of claim 1 , further comprising an integrated heat spreader at a bottom of the first die.

8 . The package of claim 1 , wherein an inactive side of the first die is covered by the first mold layer.

9 .- 16 . (canceled)

17 . A method of fabricating an integrated circuit package, the method comprising:
providing a first die in a first mold layer; attaching a first dielectric layer on a top surface of the first mold layer; providing a first patterned metal layer on the first dielectric layer; providing a pillar on the first patterned metal layer above the first dielectric layer; attaching a second die above the first dielectric layer; providing mold material above the first dielectric layer to a level above a top surface of the second die; providing a second dielectric layer above the second die; and providing a second patterned metal layer above the second dielectric layer, wherein the second patterned metal layer is coupled to the pillar, wherein the integrated circuit package comprises: the first die disposed in the first mold layer and coupled to the first dielectric layer disposed above the first mold layer; the second die disposed in a second mold layer and coupled to the second dielectric layer disposed above the second die; and a third dielectric layer disposed above the second dielectric layer and comprising pins, solder balls, or solder bumps, wherein the pillar is disposed through the second mold layer and coupled to the first patterned metal layer disposed above the first dielectric layer, the first patterned metal layer being coupled to the first die, wherein the pillar is coupled to the second patterned metal layer disposed above the second dielectric layer, the second patterned metal layer being coupled to the second die and at least one of the solder balls, the solder bumps, or the pins, and wherein the pillar is located between the first patterned metal layer and the second patterned metal layer.

18 . The method of claim 17 , further comprising providing the third dielectric layer above the second dielectric layer.

19 . The method of claim 17 , further comprising connecting input/output pads on the third dielectric layer to the second patterned metal layer.

20 . The method of claim 19 , further comprising providing the solder bumps, the solder balls, or the pins on the input/output pads on the third dielectric layer.

21 . A package, comprising:
a first die disposed in a first mold layer and coupled to a first dielectric layer disposed above the first mold layer; a second die disposed in a second mold layer and coupled to a second dielectric layer, the second dielectric layer disposed above the second die and not disposed above the second mold layer; and a third dielectric layer disposed above the second dielectric layer and comprising pins, solder balls, or solder bumps, wherein a pillar is disposed through the second mold layer and coupled to a first metal layer disposed above the first dielectric layer, the first metal layer being coupled to the first die, and wherein the pillar is coupled to a second metal layer disposed above the second dielectric layer, the second metal layer being coupled to the second die and at least one of the solder balls, solder bumps or pins.

22 . The package of claim 21 , further comprising:
a first via disposed through the first dielectric layer to a first pad disposed on the first die.

23 . The package of claim 21 , wherein the first die and the first mold layer are part of a reconstituted wafer.

24 . The package of claim 21 , wherein the first die, the first mold layer, the first dielectric layer, the second die, the second dielectric layer, and the second mold layer are part of a reconstituted wafer.

25 . The package of claim 21 , wherein the first die, the first mold layer, the first dielectric layer, the second die, and the second mold layer are part of a reconstituted wafer, wherein the second dielectric layer is above the second mold layer.

26 . The package of claim 25 , further comprising:
a third dielectric layer disposed below the second dielectric layer and above the second die, the third dielectric layer having an area, the area being the same as an area of the second die.

27 . The package of claim 21 , further comprising an integrated heat spreader at a bottom of the first die.

28 . The package of claim 21 , wherein an inactive side of the first die is covered by the first mold layer.

Assignees

• Broadcom Corp

Inventors

• Zhao Sam Ziqun
• Khan Rezaur Rahman

Classifications

• H10W90/736

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/291

  characterised by containers, encapsulations, or other housings for the stacked chips · CPC title

• H10W90/288

  characterised by arrangements for thermal management of the stacked chips · CPC title

• H10W90/28

  the stacked chips having different sizes, e.g. chip stacks having a pyramidal shape · CPC title