Embedding diamond and other ceramic media into metal substrates to form thermal interface materials

US2017301605A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2017301605-A1
Application numberUS-201615098597-A
CountryUS
Kind codeA1
Filing dateApr 14, 2016
Priority dateApr 14, 2016
Publication dateOct 19, 2017
Grant date

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A multi-layer structure includes a substrate with a surface and with particles partially covering and partially embedded in the surface. The particles have high thermal conductivity and low electrical conductivity. A dielectric layer on the surface partially covers the partially embedded particles. A metal layer on the dielectric layer covering the partially covered particles forms a thermal interface material (TIM) for electronic packaging applications.

First claim

Opening claim text (preview).

1 . A multi-layer thermal interface structure comprising: a metal substrate; a layer of particles partially covering and partially embedded in a top surface layer of the substrate, wherein the particles have high thermal conductivity and low electrical conductivity; a dielectric layer on the top surface layer of the substrate covering the surface between the partially embedded particles and partially covering the particles; and a metal layer on the dielectric layer covering the partially embedded particles. 2 . The structure of claim 1 , wherein the metal substrate comprises nickel, titanium, aluminum, copper, cobalt, tungsten, or alloys thereof, or mixtures thereof. 3 . The structure of claim 2 , wherein the metal substrate is a nickel alloy. 4 . The structure of claim 2 , wherein the metal substrate is a titanium alloy. 5 . The structure of claim 1 , wherein the particles are composed of diamond, boron nitride, silicon nitride or silicon carbide. 6 . The structure of claim 1 , wherein the dielectric layer is a polymer with electrical resistivity greater than 10 6 ohm-cm. 7 . The structure of claim 6 , wherein the polymer is a polyimide, polyethylene, nylon, spin on glass, and polyester. 8 . The structure of claim 5 , wherein the particles have a diameter of from 1 micron to 100 microns. 9 . A method of forming a multi-layer thermal interface structure with a high thermal conductivity and low electrical conductivity on a metal substrate comprising: partially covering a top surface of the substrate with high thermal conductivity, low electrical conductivity particles; partially melting the top surface of the substrate, thereby causing the particles to sink into the molten layer; allowing the molten layer to solidify to embed the particles in the substrate layer; partially covering the space around the partially embedded particles and partially covering the partially embedded particles with a dielectric material; and covering the partially covered particles with a metal layer. 10 . The method of claim 9 , wherein the high thermal conductivity, low electrical conductivity particles are composed of diamond, boron nitride, silicon nitride or silicon carbide. 11 . The method of claim 9 , wherein the high thermal conductivity, low electrical conductivity particles have a diameter of from 1 micron to 100 microns. 12 . The method of claim 9 , wherein the surface coverage of the high thermal conductivity, low electrical conductivity particles on the substrate is from about 20% to about 90%. 13 . The method of claim 12 , wherein the surface coverage of the high thermal conductivity, low electrical conductivity particles on the substrate is from about 30% to about 75%. 14 . The method of claim 9 , wherein the metal substrate comprises nickel, titanium, aluminum, copper, cobalt, tungsten, or alloys thereof, or mixtures thereof. 15 . The method of claim 14 , wherein the metal substrate is a nickel alloy 16 . The method of claim 9 , wherein partially melting the top surface of the substrate comprises laser melting, RF induction melting, infrared melting, electric arc melting and plasma melting. 17 . The method of claim 9 , wherein the dielectric material is a polyimide, polyethylene, nylon, spin on glass, and polyester. 18 . The method of claim 9 , wherein the dielectric material is a polymer with electrical resistivity greater than 10 6 ohm-cm. 19 . The method of claim 9 , wherein partially covering a top surface of the substrate with high thermal conductivity, low electrical conductivity particles and partially melting the top surface of the substrate comprises an additive manufacturing process. 20 . The method of claim 19 , wherein the additive manufacturing process comprises laser engineered net shaping (LENS), direct light manufacturing, selective laser melting (SLM), direct laser melting (DLM), laser based additive manufacturing (LBAM), and radio frequency induction melting

Assignees

Inventors

Classifications

  • of conductive package substrates serving as an interconnection, e.g. of metal plates (manufacture or treatment of leadframes H10W70/04) · CPC title

  • Ceramics or glasses (H10W40/254, H10W40/257, H10W40/255, H10W40/251, H10W40/253 take precedence) · CPC title

  • Metallic materials (H10W40/254, H10W40/257, H10W40/255, H10W40/251, H10W40/253 take precedence) · CPC title

  • Diamond · CPC title

  • Organics · CPC title

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What does patent US2017301605A1 cover?
A multi-layer structure includes a substrate with a surface and with particles partially covering and partially embedded in the surface. The particles have high thermal conductivity and low electrical conductivity. A dielectric layer on the surface partially covers the partially embedded particles. A metal layer on the dielectric layer covering the partially covered particles forms a thermal in…
Who is the assignee on this patent?
Hamilton Sundstrand Corp
What technology area does this patent fall under?
Primary CPC classification H10W40/255. Mapped technology areas include Electricity.
When was this patent published?
Publication date Thu Oct 19 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).