Thin film transistor, method for manufacturing the same, array substrate and display device

Patent metadata

Field	Value
Publication number	US-2017288060-A1
Application number	US-201615317251-A
Country	US
Kind code	A1
Filing date	Feb 24, 2016
Priority date	Sep 23, 2015
Publication date	Oct 5, 2017
Grant date	—

Abstract

A TFT is provided. The TFT includes an active layer, and the active layer includes a first active layer and a second active layer. The second active layer is made of the oxide semiconductor material, and the first active layer has conductivity greater than conductivity of the second active layer.

First claim

1 . A thin film transistor (TFT), comprising an active layer, wherein the active layer includes a first active layer and a second active layer, the second active layer is made of an oxide semiconductor material, and the first active layer has conductivity greater than conductivity of the second active layer.

2 . The TFT according to claim 1 , wherein the active layer comprises one first active layer and one second active layer.

3 . The TFT according to claim 2 , further comprising a source electrode and a drain electrode, wherein the first active layer is arranged closer to the source electrode and the drain electrode than the second active layer.

4 . The TFT according to claim 2 , further comprising a source electrode and a drain electrode, wherein the second active layer is arranged closer to the source electrode and the drain electrode than the first active layer, and an etch stop layer is formed on a surface of the second active layer.

5 . The TFT according to claim 1 , further comprising a source electrode and a drain electrode, wherein the active layer comprises one first active layer and two second active layers, the first active layer is arranged between the two second active layers, and an etch stop layer is formed on a surface of the second active layer adjacent to the source electrode and the drain electrode.

6 . The TFT according to claim 1 , wherein the first active layer is arranged at a position corresponding to a TFT channel.

7 . The TFT according to claim 1 , wherein the first active layer is made of at least one material selected from the group consisting of indium tin oxide, indium zinc oxide, stannic dioxide, indium trioxide, zinc oxide and carbon nano tube, and the second active layer is made of at least one material selected from the group consisting of indium gallium zinc oxide, cadmium oxide and aluminium oxide.

8 . The TFT according to claim 1 , wherein the first active layer has a thickness of 100 Å to 4000 Å.

9 . A method for manufacturing a thin film transistor (TFT), comprising a step of forming an active layer on a base substrate, wherein the step of forming the active layer on the base substrate comprises forming a first active layer and a second active layer on the base substrate, the second active layer is made of an oxide semiconductor material, and the first active layer has conductivity greater than conductivity of the second active layer.

10 . The method according to claim 9 , wherein the step of forming the first active layer and the second active layer on the base substrate comprises forming one first active layer and one second active layer on the base substrate.

11 . The method according to claim 10 , further comprising forming a source electrode and a drain electrode on the base substrate, wherein the first active layer is arranged closer to the source electrode and the drain electrode than the second active layer.

12 . The method according to claim 10 , further comprising forming a source electrode and a drain electrode on the base substrate, wherein the second active layer is arranged closer to the source electrode and the drain electrode than the first active layer, and prior to the step of forming the source electrode and the drain electrode on the base substrate, the method further comprises forming an etch stop layer on a surface of the second active layer.

13 . The method according to claim 9 , further comprising forming a source electrode and a drain electrode on the base substrate, wherein the step of forming the first active layer and the second active layer on the base substrate comprises forming one first active layer and two second active layers on the base substrate, the first active layer is arranged between the two second active layers, and an etch stop layer is formed on a surface of the second active layer adjacent to the source electrode and the drain electrode.

14 . The method according to claim 9 , wherein the first active layer is made of at least one material selected from the group consisting of indium tin oxide, indium zinc oxide, stannic dioxide, indium trioxide, zinc oxide and carbon nano tube, and the second active layer is made of at least one material selected from the group consisting of indium gallium zinc oxide, cadmium oxide and aluminium oxide.

15 . An array substrate, comprising the TFT according to claim 1 .

16 . A display device, comprising the array substrate according to claim 15 .

Assignees

• Boe Technology Group Co Ltd
• Hefei Boe Optoelectronics Tech

Inventors

• Park Kuhyun

Classifications

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H01L29/66969

  Electricity · mapped topic

• H01L29/7869 Primary

  Electricity · mapped topic

• H01L29/78696

  Electricity · mapped topic

• H01L27/1225

  Electricity · mapped topic