Method for layout design and structure with inter-layer vias

Patent metadata

Field	Value
Publication number	US-2017278789-A1
Application number	US-201715619959-A
Country	US
Kind code	A1
Filing date	Jun 12, 2017
Priority date	Mar 20, 2014
Publication date	Sep 28, 2017
Grant date	—

Abstract

A computer implemented layout method for an integrated circuit (IC) structure and IC structure are provided. Such a method includes: placing a power supply rail pattern in a first device layer of the IC; bundling, for purposes of placement, a voltage level shifter and one or more inter-layer vias together as an integral unit; and placing the integral unit in the first device layer of the IC design such that one or more metal line patterns in the voltage level shifter are located parallel to albeit without overlapping the power supply rail pattern. The placing the integral unit forms a direct electrical connection channel between the voltage level shifter and a metal pattern in a second device layer of the IC design. At least one of the placing operations is performed using a layout generating machine.

First claim

What is claimed is:

1 . A computer implemented layout method, the method comprising:
placing a power supply rail pattern in a first device layer of an integrated circuit (IC); bundling, for purposes of placement, a voltage level shifter and one or more inter-layer vias together as an integral unit; and placing the integral unit of the voltage level shifter and the one or more inter-layer vias in the first device layer of the IC design such that one or more metal line patterns in the voltage level shifter are located parallel to albeit without overlapping the power supply rail pattern; wherein:
the placing the integral unit of the voltage level shifter and the one or more inter-layer vias forms a direct electrical connection channel between the voltage level shifter and a metal pattern in a second device layer of the IC design; and
at least one of the above placing operations is performed using a layout generating machine.

2 . The method of claim 1 , wherein the voltage level shifter includes at least one active component.

3 . The method of claim 1 , wherein the voltage level shifter and the one or more inter-layer vias are placed in a location within the first device layer of the IC design, and wherein the location within the first device layer corresponds to a location within the second device layer.

4 . The method of claim 3 , further comprising placing a power supply line in the first device layer to the voltage level shifter.

5 . The method of claim 3 , wherein the first device layer is placed with a first power supply line and the second device layer is placed with a second power supply line.

6 . The method of claim 1 , wherein a footprint of each inter-layer via of the one or more inter-layer vias is at least one order of magnitude smaller than a footprint of the voltage level shifter.

7 . The method of claim 1 , wherein at least one of the one or more inter-layer vias is configured to carry a power supply voltage, an analog signal or a logic signal.

8 . The method of claim 1 , further comprising:
placing a plurality of circuits in the IC design, at least one of the plurality of circuits being connected to the voltage level shifter; evaluating routing and timing violations of the IC design; and relocating the voltage level shifter and the metal pattern to meet a predetermined routing rule and timing goal.

9 . The method of claim 1 , wherein the IC design is a monolithic three dimensional IC (3DIC) structure.

10 . The method of claim 1 , wherein:
the power supply rail pattern in the first device layer represents an intra-layer connection of the first device layer; the metal pattern in the second device layer represents an intra-layer connection of the second device layer; and the integral unit of the voltage level shifter and the one or more inter-layer vias represents an inter-layer connection between the first and second device layers.

11 . A computer implemented layout method, the method comprising:
bundling, for purposes of placement, a voltage level shifter and an inter-layer via together as an integral unit; placing the integral unit of the voltage level shifter and the inter-layer via in a first device layer of an integrated circuit (IC) design, the first device layer including at least one active component; placing a connection between the voltage level shifter and a power supply rail within the first device layer; and wherein:
the placing the integral unit of the voltage level shifter and the inter-layer via forms a direct electrical connection channel between the first device layer and a second device layer of the IC design which thereby provides a level-shifted version of voltage on the power supply rail from the first device layer to the second device layer; and
at least one of the above placing operations is performed using a layout generating machine.

12 . The method of claim 11 , wherein a footprint of the inter-layer via is at least one order of magnitude smaller than a footprint of the voltage level shifter.

13 . The method of claim 11 , wherein the inter-layer via is configured to carry a power supply voltage.

14 . The method of claim 11 , wherein the inter-layer via is configured to carry an analog or a logic signal.

15 . The method of claim 11 , further comprising:
placing a plurality of circuits in the IC design, at least one of the plurality of circuits being connected to the voltage level shifter.

16 . A three dimensional integrated circuit (3DIC) structure comprising:
a circuit cell in a first device layer of the 3DIC structure; and an inter-layer via connecting the circuit cell in the first device layer at a predetermined location and connecting a metal pattern in a second device layer of the 3DIC structure, the predetermined location being within a cell boundary of the circuit cell in the first device layer of the 3DIC structure; wherein a footprint of the inter-layer via is at least one order of magnitude smaller than a footprint of the circuit cell.

17 . The integrated circuit of claim 16 , wherein the predetermined location within the first device layer corresponds to a location within the second device layer.

18 . The integrated circuit of claim 16 , wherein the inter-layer via is configured to carry a power supply voltage, an analog signal, or a logic signal.

19 . The integrated circuit of claim 16 , wherein the inter-layer via is vertical or substantially vertical to the first device layer and the second device layer.

20 . The integrated circuit of claim 16 , wherein:
a footprint of the inter-layer via is two orders of magnitude smaller than a footprint of a through-silicon-via.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chuang Yi-Lin
• Chen Ching-Fang
• Shen Jia-Jye

Classifications

• H10W20/427

  Power or ground buses · CPC title

• H10W20/42 Primary

  Vias, e.g. via plugs · CPC title

• G06F30/398

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• G06F30/392

  Floor-planning or layout, e.g. partitioning or placement · CPC title

• G06F30/394

  Routing (G06F30/396 takes precedence) · CPC title