Method for layout design and structure with inter-layer vias

Patent metadata

Field	Value
Publication number	US-9679840-B2
Application number	US-201414220751-A
Country	US
Kind code	B2
Filing date	Mar 20, 2014
Priority date	Mar 20, 2014
Publication date	Jun 13, 2017
Grant date	Jun 13, 2017

Abstract

A computer implemented layout method for an integrated circuit (IC) structure and IC structure are provided. The layout method can include placing a circuit cell and an inter-layer via together in a first device layer of the IC structure, and placing a metal pattern in a second device layer of the IC structure. The inter-layer via and the metal pattern may be configured to form a direct connection channel for the circuit cell and the metal pattern.

First claim

What is claimed is:

1. A computer implemented layout method, the method comprising:
bundling, for purposes of placement, a circuit cell and an inter-layer via together as an integral unit;
placing the integral unit of the circuit cell and the inter-layer via in a first device layer of an integrated circuit (IC) design; and
placing a metal pattern in a second device layer of the IC design,
wherein the placing the integral unit of the circuit cell and the inter-layer via forms a direct electrical connection channel between the circuit cell and the metal pattern, and at least one of the above placing operations is performed using a layout generating machine.

2. The method of claim 1 , wherein the circuit cell includes at least one active component.

3. The method of claim 1 , wherein the circuit cell and the inter-layer via are placed in a location within the first device layer of the IC design, and wherein the location within the first device layer corresponds to a location within the second device layer.

4. The method of claim 3 , further comprising placing a power supply line in the first device layer to the circuit cell.

5. The method of claim 3 , wherein the first device layer is placed with a first power supply line and the second device layer is placed with a second power supply line.

6. The method of claim 1 , wherein the circuit cell includes a voltage level shifter.

7. The method of claim 1 , wherein the inter-layer via is configured to carry a power supply voltage, an analog signal or a logic signal.

8. The method of claim 1 , further comprising:
placing a plurality of circuits in the IC design, at least one of the plurality of circuits being connected to the circuit cell;
evaluating routing and timing violations of the IC design; and
relocating the circuit cell and the metal pattern to meet a predetermined routing rule and timing goal.

9. The method of claim 1 , wherein the IC structure is a monolithic three dimensional IC (3DIC) structure.

10. A computer implemented layout method, the method comprising:
bundling, for purposes of placement, a circuit cell and the inter-layer via together as an integral unit;
placing the integral unit of the circuit cell and the inter-layer via in a first device layer of an integrated circuit (IC) design, the first device layer including at least one active component;
placing a connection between the circuit cell and a power supply rail within the first device layer; and
placing a metal pattern in a second device layer of the IC design, the second device layer including a second power supply voltage connection,
wherein the placing the integral unit of the circuit cell and the inter-layer via and the metal pattern forms a direct electrical connection channel between the first device layer and the second device layer;
evaluating routing and timing violations of the IC design; and
relocating the circuit cell along with the metal pattern to meet a predetermined routing rule and timing goal, wherein at least one of the above placing operations is performed using a layout generating machine.

11. The method of claim 10 , wherein the circuit cell includes a voltage level shifter.

12. The method of claim 10 , wherein the inter-layer via is configured to carry a power supply voltage.

13. The method of claim 10 , wherein the inter-layer via is configured to carry an analog or a logic signal.

14. The method of claim 10 , further comprising:
placing a plurality of circuits in the IC design, at least one of the plurality of circuits being connected to the circuit cell.

15. The method of claim 10 , further comprising
bundling, as an integral unit for purposes of placement, the inter-layer via and the circuit cell, which includes the voltage level shifter; and
wherein the placing a circuit cell and an inter-layer via places the integral unit of the inter-layer via and the circuit cell, which includes the voltage level shifter.

16. A three dimensional integrated circuit (3DIC) structure comprising:
a circuit cell in a first device layer of the 3DIC structure, the circuit cell includes a voltage level shifter;
a metal pattern in a second device layer of the 3DIC structure; and
an inter-layer via connecting the voltage level shifter of the circuit cell in the first device layer at a predetermined location and connecting the metal pattern in the second device layer of the 3DIC structure, the predetermined location being within a cell boundary of the circuit cell in the first device layer of the 3DIC structure;
wherein a footprint of the inter-layer via is at least one order of magnitude smaller than a footprint of the circuit cell.

17. The integrated circuit of claim 16 , wherein the predetermined location within the first device layer corresponds to a location within the second device layer.

18. The integrated circuit of claim 16 , wherein the inter-layer via is configured to carry a power supply voltage, an analog signal, or a logic signal.

19. The integrated circuit of claim 16 , wherein the inter-layer via is vertical or substantially vertical to the first device layer and the second device layer.

20. The integrated circuit of claim 16 , wherein:
a footprint of the inter-layer via is two orders of magnitude smaller than a footprint of a through-silicon-via.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chuang Yi-Lin
• Chen Ching-Fang
• Shen Jia-Jye

Classifications

• H10W20/427

  Power or ground buses · CPC title

• H10W20/42 Primary

  Vias, e.g. via plugs · CPC title

• G06F2119/12

  Timing analysis or timing optimisation · CPC title

• G06F30/394

  Routing (G06F30/396 takes precedence) · CPC title

• G06F30/398

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title