Semiconductor devices and methods of fabricating the same

Patent metadata

Field	Value
Publication number	US-2017271479-A1
Application number	US-201715612338-A
Country	US
Kind code	A1
Filing date	Jun 2, 2017
Priority date	Apr 10, 2015
Publication date	Sep 21, 2017
Grant date	—

Abstract

A method of fabricating a semiconductor device is provided as follows. A source/drain pattern is formed on a substrate. The source/drain pattern contains silicon atoms and germanium atoms. At least one germanium atom is removed from the germanium atoms of the source/drain pattern.

First claim

What is claimed is:

1 . A semiconductor device, comprising:
active patterns disposed on a substrate, wherein each of the active patterns, extending in a first direction, has a first region and a recessed region; a device isolation pattern provided on the substrate to cover lower sidewalls of the active patterns; a gate pattern disposed on the first region of the active pattern, wherein the gate pattern extends in a second direction different from the first direction; a source/drain pattern disposed on the recessed regions of the active patterns; and a capping pattern covering the source/drain pattern, wherein the capping pattern has a substantially uniform thickness, wherein the source/drain pattern comprises: first portions provided on the recess regions of the active patterns; and a second portion provided on the device isolation pattern and interposed between the first portions.

2 . The semiconductor device of claim 1 ,
wherein the capping pattern comprises a first portion, a second portion connected to the first portion and a third portion connected to the first and second portions, and the first, second and third portions have substantially a same thickness.

3 . The semiconductor device of claim 2 ,
wherein the first portions of source/drain pattern contact the first and second portions of the capping pattern and has a {111} crystal plane, and the second portion of the source/drain pattern contacts the third portion of the capping pattern and has a {100} crystal plane and a {110} crystal plane.

4 . The semiconductor device of claim 2 ,
wherein the source/drain pattern and the capping pattern comprise a plurality of germanium atoms, and the capping pattern has less germanium atoms than the source/drain pattern.

5 . A semiconductor device, comprising:
an active pattern disposed on a substrate and extended in a first direction; a gate pattern disposed on a first region of the active pattern and extended in a second direction different from the first direction; a source/drain pattern disposed on a second region of the active pattern, wherein the second region of the active pattern is adjacent to the gate pattern and the source/drain pattern has a first concentration of germanium atoms; a first capping pattern covering the source/drain pattern, wherein the first capping pattern has a second concentration of germanium atoms smaller than the first concentration and the capping pattern has a substantially uniform thickness; and a contact plug penetrating the first capping pattern to be in contact with the source/drain pattern.

6 . The semiconductor device of claim 5 ,
wherein a difference between the second concentration and the first concentration is about 3 atomic percent or more.

7 . The semiconductor device of claim 5 ,
wherein the second region of the active pattern is recessed, and the source/drain pattern is disposed in the recessed second region.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Jinbum
• Park Jaeyoung
• Lee Donghun
• Yoo Jeongho
• Yoon Jieon
• Lee Kwan Heum
• Lee Choeun
• Koo Bonyoung

Classifications

• H10P95/94

  Hydrogenation or deuterisation, e.g. using atomic hydrogen from a plasma · CPC title

• H01L21/3003

  Electricity · mapped topic

• H01L29/045

  Electricity · mapped topic

• H01L29/66545

  Electricity · mapped topic

• H01L29/78

  Electricity · mapped topic