Method for fabrication of a field-effect with reduced stray capacitance

Patent metadata

Field	Value
Publication number	US-2017271470-A1
Application number	US-201715464763-A
Country	US
Kind code	A1
Filing date	Mar 21, 2017
Priority date	Mar 21, 2016
Publication date	Sep 21, 2017
Grant date	—

Abstract

A method of fabrication, including the steps for supplying a substrate including a layer of semiconductor material covered by a sacrificial gate including a sacrificial gate insulator including a middle part, and edges covered by sacrificial spacers and having a thickness tox; removal of the sacrificial gate insulator and the sacrificial gate material; formation of a conformal deposition of thickness thk of dielectric material inside of the groove formed in order to form a gate insulator, with tox>thk≧tox/2; formation of a gate electrode within the groove; removal of the sacrificial spacers so as to open up edges of the gate insulator layer; formation of spacers on the edges of the gate insulator layer on either side of the gate electrode, these spacers having a dielectric constant at the most equal to 3.5.

First claim

1 . A method for fabrication of a field-effect transistor starting from a substrate comprising a layer of semiconductor material covered by a sacrificial gate, the sacrificial gate comprising a sacrificial gate insulator comprising:
a middle part covered by a sacrificial gate material, and edges covered by sacrificial spacers, the said edges having a thickness tox; the method comprising the steps for: removing the sacrificial gate material and the sacrificial gate insulator so as to create a groove between and under the sacrificial spacers; forming a conformal deposition of thickness thk of dielectric material inside of the groove on the internal faces of the sacrificial spacers and on the layer of semiconductor material and under the sacrificial spacers in order to form a gate insulator layer, the said dielectric material having a dielectric constant equal to at least 4, and
tox>thk≧tox/ 2;
forming a gate electrode on the gate insulator layer within the groove; removing the sacrificial spacers and the deposition of dielectric material formed on the internal faces of the sacrificial spacers, in such a manner as to open up edges of the gate insulator layer; forming spacers on the edges of the gate insulator layer on either side of the gate electrode, these spacers having a dielectric constant at the most equal to 3.5.

2 . The method for fabrication of a field-effect transistor according to claim 1 , in which Rk=Ehk/Elk≧2, with Ehk the dielectric constant of the dielectric material deposited for forming the gate insulator layer and Elk the dielectric constant of the spacers formed on the edges of the gate insulator layer.

3 . The method for fabrication of a field-effect transistor according to claim 1 , in which tox is in the range between 2 and 5 nm.

4 . The method for fabrication of a field-effect transistor according to claim 1 , wherein said deposited dielectric material is selected from within the group composed of TiO 2 , Al 2 O 3 , ZrO 2 , HfO 2 , HfSiO, Ta 2 O 5 , La 2 O 3 , and of nitrides of these materials.

5 . The method for fabrication of a field-effect transistor according to claim 1 , further comprising a step for formation of source and drain contacts on either side of the gate electrode, the said contacts extending to be in line with said spacers formed on the edges of the gate insulator layer.

6 . The method for fabrication of a field-effect transistor according claim 1 , wherein said spacers formed cover the edges of the gate insulator layer.

7 . The method for fabrication of a field-effect transistor according to claim 1 , in wherein said substrate supplied comprises:
a layer of buried insulator under the layer of semiconductor material; and raised elements made of a semiconductor material disposed on either side of the sacrificial gate.

8 . The method for fabrication of a field-effect transistor according to claim 7 , wherein said spacers formed on the edges of the gate insulator layer comprise extensions over one edge of the said raised elements.

9 . The method for fabrication of a field-effect transistor according to claim 8 , wherein said extensions extend over a length in the range between 3 and 5 nm over the edge of said raised elements.

10 . The method for fabrication of a field-effect transistor according to claim 7 , comprising a prior step for deposition of the raised elements by epitaxy on either side of the sacrificial gate insulator.

11 . The method for fabrication of a field-effect transistor according to claim 1 , wherein said substrate supplied is of the bulk substrate type and comprises a doped source and drain arranged on either side of the sacrificial gate.

12 . The method for fabrication of a field-effect transistor according to claim 1 , wherein said dielectric material deposited inside of the groove is different from the material of the sacrificial spacers.

13 . The method for fabrication of a field-effect transistor according to claim 1 , further comprising the formation of a plug made of a dielectric material on the said gate electrode formed.

14 . The method for fabrication of a field-effect transistor according to claim 1 , wherein the sacrificial gate insulator is an oxide.

Assignees

• Commissariat Energie Atomique
• St Microelectronics Sa
• St Microelectronics Crolles 2 Sas
• Commissariat A I'Energie Atomique Et Aux Energies Alternatives

Inventors

• Le Royer Cyrille
• Boeuf Frederic
• Grenouillet Laurent
• Hutin Louis
• Morand Yves

Classifications

• H10W20/0698

  Local interconnections · CPC title

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H01L29/0649

  Electricity · mapped topic

• H01L23/535

  Electricity · mapped topic

• H01L21/76895

  Electricity · mapped topic