Techniques for observing an entire communication bus in operation

Patent metadata

Field	Value
Publication number	US-2017265304-A1
Application number	US-201615068474-A
Country	US
Kind code	A1
Filing date	Mar 11, 2016
Priority date	Mar 11, 2016
Publication date	Sep 14, 2017
Grant date	—

Abstract

A circuit board includes conductive traces being sandwiched by an upper insulating layer and a lower insulating layer, a first array of conductive vias extending perpendicularly to the conductive traces, the vias in the first array of conductive vias being arranged such that any two adjacent vias in a row of vias extending along any given dimension in the first array of conductive vias are equally spaced from each other, and isolation resistors embedded within the first array of conductive vias such that each isolation resistor is disposed between at least two adjacent vias in the first array of conductive vias, each isolation resistor being disposed closer to the conductive via to which the isolation resistor is coupled than all other conductive vias surrounding the isolation resistor.

First claim

1 . A circuit board, comprising:
conductive traces being sandwiched by an upper insulating layer and a lower insulating layer; a first array of conductive vias extending perpendicularly to the conductive traces, the vias in the first array of conductive vias being arranged such that any two adjacent vias in a row of vias extending along any given dimension in the first array of conductive vias are equally spaced from each other; and isolation resistors embedded within the first array of conductive vias such that each isolation resistor is disposed between at least two adjacent vias in the first array of conductive vias, wherein the conductive traces include a first group of conductive traces, each of the conductive traces in the first group of conductive traces being coupled to a different conductive via in the first array of conductive vias through one of the isolation resistors, each isolation resistor being disposed closer to the conductive via to which the isolation resistor is coupled than all other conductive vias surrounding the isolation resistor, each isolation resistor being configured to produce a copy of a signal flowing through the conductive via that is coupled to one end of the isolation resistor on the conductive trace that is coupled to an opposite end of the isolation resistor.

2 . The circuit board of claim 1 , wherein each conductive trace in the first group of conductive traces includes a conductive upper layer and a resistive lower layer, the conductive upper layer having an opening through which a portion of the resistive lower layer is exposed, the exposed portion of the resistive lower layer forming one of the isolation resistors.

3 . The circuit board of claim 2 wherein the exposed portion of the resistive layer is spaced less than 50 μm from the conductive via to which it is coupled.

4 . The circuit board of claim 1 , wherein a spacing between every two adjacent conductive vias along a row of conductive vias in the first array of conductive vias is in the range of 0.35 mm to 0.8 mm.

5 . The circuit board of claim 1 , wherein a resistance value of each embedded isolation resistor is less than 50 ohms.

6 . The circuit board of claim 1 , further comprising a first array of contact pads disposed on a surface of the circuit board, each via in the first array of conductive vias terminating at and electrically connecting to a corresponding contact pad in the first array of contact pads, wherein the circuit board is configured so that a first integrated circuit can be mounted on and electrically connected to the first array of contact pads.

7 . The circuit board of claim 1 further comprising:
a second array of conductive vias being insulated from one another; and
a second array of contact pads disposed on a surface of the circuit board, each via in the second array of conductive vias terminating at and electrically connecting to a corresponding contact pad in the second array of contact pads, the second array of contact pads being connected to the first group of conducive traces through the second array of conductive vias,
wherein the circuit board is configured so that a monitoring device can be connected to the second array of contact pads for monitoring signals on the second array of contact pads.

8 . (canceled)

9 . The circuit board of claim 7 , wherein the first array of conductive vias form part of a communication bus through which the first integrated circuit can communicate with a second integrated circuit, and during operation, each conductive trace in the first group of conductive traces carries a copy of a bus signal propagating through a corresponding one of the conductive vias in the first array of conductive vias so that the entire communication bus can be simultaneously monitored on the second array of contact pads.

10 . The circuit board of claim 7 further comprising:
a third array of contact pads on a surface of the circuit board,
a third array of conductive vias being insulated from one another; and
a third array of contact pads disposed on a surface of the circuit board, each via in the third array of conductive vias terminating at and electrically connecting to a corresponding contact pad in the third array of contact pads, the conductive traces including a second group of conducive traces, the third array of contact pads being connected to the second group of conducive traces through the third array of conductive vias,
wherein the circuit board is configured so that a second integrated circuit can be mounted on and electrically connected to the third array of contact pads.

11 . The circuit board of claim 1 , wherein the first array of conductive vias include through-vias connecting the first array of contact pads disposed on a first surface of the circuit board to corresponding contact pads in an array of contact pads disposed on a second surface of the circuit board opposite the first surface.

12 . The circuit board of claim 1 further comprising a plurality of interconnect layers stacked on top of one another, each interconnect layer being insulated from an adjacent interconnect layer,
wherein the conductive traces include multiple groups of conductive traces, each group of conductive traces being disposed in a different one of the plurality of interconnect layers, and the conductive traces in each group of conductive traces extending along the same plane,
wherein the isolation resistors are disposed in a first one of the plurality of interconnect layers, and each of the conductive traces in the group of conductive traces disposed in the first one of the plurality of interconnect layers includes a conductive upper layer and a resistive lower layer.

13 . The circuit board of claim 1 , further comprising a plurality of interconnect layers stacked on top of one another, each interconnect layer being insulated from an adjacent interconnect layer,
wherein the conductive traces include multiple groups of conductive traces, each group of conductive traces being disposed in a different one of the plurality of interconnect layers, the conductive traces in each group of conductive traces extending along the same plane, wherein the isolation resistors are disposed in two or more of the plurality of interconnect layers.

14 . A method of forming a circuit board, comprising:
forming conductive traces insulated from one another; forming multiple arrays of conductive vias extending perpendicularly to the conductive traces; and forming multiple arrays of contact pads disposed on one or more surfaces of the circuit board, the multiple arrays of contact pads including a first array of contact pads, the multiple arrays of conductive vias including a first array of conductive vias, each via in the first array of conductive vias terminating at and electrically connecting to a corresponding contact pad in the first array of contact pads, the vias in the first array of conductive vias being arranged such that any two adjacent vias in a row of vias extending along any given dimension in the first array of conductive vias are equally spaced from each other, wherein the conductive traces include a first group of conductive traces, each conductive trace in the first group of conductive traces being coupled to a different conductive via in the first array of conductive vias through an isolation resistor embedded in the first array of conductive vias adjacent the conductive via to which the isolation resistor is coupled, each isolation resistor being disposed between at least two adjacent vias in the first array of conductive vias, and each isolation resistor being disposed closer to the conductive via

Assignees

• Apple Inc

Inventors

• Mason Anne M
• Johnston Peter J
• Laliberte Christine A
• Mccarthy Dominic P
• Arnold Shawn X
• Mukherjee Souvik

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/252

  comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W90/401

  characterised by multiple insulating or insulated package substrates, interposers or RDLs · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W72/20

  Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps · CPC title