Semiconductor device and method for manufacturing the same

Patent metadata

Field	Value
Publication number	US-2017243973-A1
Application number	US-201615391888-A
Country	US
Kind code	A1
Filing date	Dec 28, 2016
Priority date	Feb 23, 2016
Publication date	Aug 24, 2017
Grant date	—

Abstract

A semiconductor device including a semiconductor substrate including a trench, the semiconductor substrate having a crystal structure; and an insulating layer covering an inner sidewall of the trench, wherein the inner sidewall of the trench has at least one plane included in a {320} family of planes of the crystal structure or at least one plane similar to the {320} family of planes.

First claim

1 - 9 . (canceled)

10 . A semiconductor device, comprising:
a semiconductor substrate including:
an active region defined by a device isolation layer; and
a trench intersecting the active region to extend into the device isolation layer, the semiconductor substrate having a crystal structure;
a gate electrode in the trench; a gate insulating layer between the gate electrode and the semiconductor substrate; and source/drain regions at both sides of the trench, wherein the trench includes an inner sidewall that has at least one plane included in a {320} family of planes of the crystal structure or at least one plane similar to the {320} family of planes.

11 . The semiconductor device as claimed in claim 10 , wherein a top surface of the semiconductor substrate has at least one plane included in a {100} family of planes of the crystal structure.

12 . The semiconductor device as claimed in claim 10 , wherein the semiconductor substrate has a diamond crystal structure.

13 . The semiconductor device as claimed in claim 12 , wherein the semiconductor substrate is a single-crystalline silicon substrate or a single-crystalline germanium substrate.

14 . The semiconductor device as claimed in claim 10 , wherein:
the gate insulating layer is in contact with the semiconductor substrate, and the gate insulating layer includes a silicon oxide layer or a silicon oxynitride layer.

15 . The semiconductor device as claimed in claim 10 , wherein:
a top surface of the semiconductor substrate has a (001) plane of the crystal structure, and the trench extends in a [−230] direction of the crystal structure.

16 . The semiconductor device as claimed in claim 10 , wherein:
the trench extends in a first direction when viewed in a plan view, the active region has a rectangular shape having a long axis in a second direction when viewed in a plan view, and an angle between the first direction and the second direction ranges from 65.38 degrees to 69.38 degrees when viewed in a plan view.

17 . The semiconductor device as claimed in claim 16 , wherein:
the active region includes a sidewall extending in the second direction, and the sidewall of the active region has a (3-20) plane of the crystal structure.

18 . The semiconductor device as claimed in claim 16 , wherein:
the first direction is a [−230] direction of the crystal structure, and the second direction is a [230] direction of the crystal structure.

19 . The semiconductor device as claimed in claim 10 , further comprising:
a bit line electrically connected to one of the source/drain regions; and a data storage part electrically connected to the other of the source/drain regions.

20 . (canceled)

21 . A semiconductor device, comprising:
a semiconductor substrate having a crystal structure and including an active pattern defined by a device isolation layer, the active pattern including a sidewall having at least one plane included in a {320} family of planes of the crystal structure or at least one plane similar to the {320} family of planes; a gate electrode intersecting the active pattern; a gate insulating layer between the gate electrode and the active pattern; and source/drain regions at both sides of the gate electrode.

22 . The semiconductor device as claimed in claim 21 , wherein a top surface of the semiconductor substrate has at least one plane included in a {100} family of planes of the crystal structure.

23 . The semiconductor device as claimed in claim 21 , wherein the semiconductor substrate has a diamond crystal structure.

24 . The semiconductor device as claimed in claim 21 , wherein:
the gate insulating layer is in contact with the semiconductor substrate, and the gate insulating layer includes a silicon oxide layer or a silicon oxynitride layer.

25 . The semiconductor device as claimed in claim 21 , wherein:
a top surface of the semiconductor substrate has a (001) plane of the crystal structure, and the active pattern extends in a [−230] direction of the crystal structure.

26 - 30 . (canceled)

31 . A semiconductor device, comprising:
a semiconductor substrate including a trench, the semiconductor substrate having a crystal structure; and an insulating layer covering an inner sidewall of the trench, wherein the inner sidewall of the trench has at least one plane included in a {320} family of planes of the crystal structure or a plane having an angle within 2 degrees of the {320} family of planes of the crystal structure.

32 . The semiconductor device as claimed in claim 31 , wherein a top surface of the semiconductor substrate has at least one plane included in a {100} family of planes of the crystal structure.

33 . The semiconductor device as claimed in claim 32 , wherein the trench extends in one direction included in a <230> family of directions of the crystal structure.

34 . The semiconductor device as claimed in claim 31 , wherein:
a top surface of the semiconductor substrate has a (001) plane of the crystal structure, the inner sidewall of the trench has a (320) plane of the crystal structure, and the trench extends in a [−230] direction of the crystal structure.

35 . The semiconductor device as claimed in claim 31 , wherein:
the insulating layer is in contact with the inner sidewall of the trench, and the insulating layer includes a silicon oxide layer or a silicon oxynitride layer.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Sungsam
• Kim Junsoo
• Ahn Hyoshin
• Yamada Satoru
• Jeon Joohyun
• Jeong Moonyoung
• Chung Chunhyung
• Cho Min Hee
• Chae Kyo-Suk
• CHOI Eunae

Classifications

• H10W70/68

  Shapes or dispositions thereof · CPC title

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/014 Primary

  using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H01L29/045

  Electricity · mapped topic

• H01L29/4236

  Electricity · mapped topic