Methods and systems to enhance process uniformity

Patent metadata

Field	Value
Publication number	US-2017229291-A1
Application number	US-201715581446-A
Country	US
Kind code	A1
Filing date	Apr 28, 2017
Priority date	Nov 26, 2014
Publication date	Aug 10, 2017
Grant date	—

Abstract

A semiconductor processing chamber may include a remote plasma region, and a processing region fluidly coupled with the remote plasma region. The processing region may be configured to house a substrate on a support pedestal. The support pedestal may include a first material at an interior region of the pedestal. The support pedestal may also include an annular member coupled with a distal portion of the pedestal or at an exterior region of the pedestal. The annular member may include a second material different from the first material.

First claim

1 . A semiconductor processing chamber comprising:
a support pedestal; a remote plasma region; and a processing region fluidly coupled with the remote plasma region, wherein:
the processing region is configured to house a substrate on the support pedestal,
the support pedestal comprises a first material at an interior region of the support pedestal,
the support pedestal defines at least one recessed ledge,
the support pedestal comprises an annular member coupled with a distal portion of the support pedestal, and
the annular member comprises a second material different from the first material.

2 . The semiconductor processing chamber of claim 1 , wherein the recessed ledge is defined in a top surface of the support pedestal.

3 . The semiconductor processing chamber of claim 1 , wherein the annular member comprises a first material plated with the second material.

4 . The semiconductor processing chamber of claim 3 , wherein the second material is not disposed on surfaces of the annular member in contact with the support pedestal.

5 . The semiconductor processing chamber of claim 1 , wherein the annular member extends along an external edge of the support pedestal towards a stem region of the support pedestal.

6 . The semiconductor processing chamber of claim 1 , wherein the support pedestal comprises an upper surface, and wherein the annular member extends vertically above the upper surface of the support pedestal.

7 . The semiconductor processing chamber of claim 1 , wherein the annular member is coupled with the support pedestal at an edge region beyond outer dimensions of a centrally located substrate region.

8 . The semiconductor processing chamber of claim 1 , wherein fluorine has a higher affinity to the second material than the first material.

9 . The semiconductor processing chamber of claim 8 , wherein the second material comprises nickel or platinum.

10 . The semiconductor processing chamber of claim 9 , wherein the second material comprises nickel or platinum.

11 . The semiconductor processing chamber of claim 1 , wherein the processing region is at least partially defined by a sidewall and wherein the sidewall comprises the second material.

12 . The semiconductor processing chamber of claim 1 , wherein a sidewall heating element is embedded in a chamber sidewall proximate a showerhead.

13 . The semiconductor processing chamber of claim 12 , wherein the support pedestal further comprises a pedestal temperature control.

14 . The semiconductor processing chamber of claim 13 , wherein the pedestal temperature control is configured to maintain the support pedestal at a first temperature, wherein the sidewall heating element is configured to maintain the annular member at a second temperature, and wherein the second temperature is greater than the first temperature.

15 . A semiconductor processing chamber comprising:
a remote plasma region; and a processing region fluidly coupled with the remote plasma region, wherein:
the processing region is at least partially defined by each of a showerhead, a substrate support pedestal comprising a first material, and a sidewall,
the sidewall includes a liner on an interior chamber surface comprising a second material different from the first material, and
a resistive heater is embedded in the sidewall.

16 . The semiconductor processing chamber of claim 15 , wherein the support pedestal comprises a platform coupled with a stem, and wherein the liner is disposed on the sidewall from the showerhead to a distance proximate an intersection between the coupled platform and stem.

17 . The semiconductor processing chamber of claim 15 , wherein the support pedestal comprises a temperature control, and wherein the temperature control is configured to maintain a substrate temperature at least 20° C. below a sidewall temperature maintained by the resistive heater.

18 . The semiconductor processing chamber of claim 15 , wherein the resistive heater is located within the sidewall proximate the showerhead.

19 . The semiconductor processing chamber of claim 15 , wherein the liner is positioned along the sidewall adjacent the showerhead.

20 . The semiconductor processing chamber of claim 19 , wherein the liner contacts the showerhead.

Assignees

• Applied Materials Inc

Inventors

• Singh Saravjeet
• Tso Alan
• Zhang Jingchun
• Li Zihui
• Zhang Hanshen
• Lubomirsky Dmitry

Classifications

• H10P72/0421 Primary

  for drying etching · CPC title

• H01J37/32715

  Workpiece holder · CPC title

• H01J37/32449

  Gas control, e.g. control of the gas flow · CPC title

• H01J37/32357 Primary

  Generation remote from the workpiece, e.g. down-stream · CPC title

• H01J2237/334

  Etching · CPC title