Display panel, array substrate, and fabrication method thereof

Patent metadata

Field	Value
Publication number	US-2017221925-A1
Application number	US-201715492035-A
Country	US
Kind code	A1
Filing date	Apr 20, 2017
Priority date	Dec 13, 2016
Publication date	Aug 3, 2017
Grant date	—

Abstract

The disclosure provides a display panel, an array substrate and a fabrication method thereof. The fabrication method of the array substrate includes forming a plurality of first thin film transistors and a plurality of second thin film transistors on the first substrate. The etch stopper layer of the second thin film transistor is different from an etch stopper layer of the first thin film transistor, and a threshold voltage of the second thin film transistor is higher than a threshold voltage of the first thin film transistor. By using the disclosed thin film transistors to form the gate driving circuit, the second thin film transistor with a high threshold voltage can be used as the driving signal outputting transistor. The abnormal multi-pulse of the gate driving circuit and the display panel caused by the low threshold voltage of the second thin film transistors may be therefore avoided.

First claim

What is claimed is:

1 . A method for fabricating an array substrate, comprising:
providing a first substrate; and forming a plurality of first thin film transistors and a plurality of second thin film transistors on the first substrate, wherein an etch stopper layer of the second thin film transistor is different from an etch stopper layer of the first thin film transistor, and a threshold voltage of the second thin film transistor is higher than a threshold voltage of the first thin film transistor.

2 . The method for fabricating an array substrate according to claim 1 , wherein the first substrate comprises a display region and a function region, after forming the plurality of first thin film transistors and the plurality of second thin film transistors on the first substrate, further comprising:
forming a pixel driving layer by using the thin film transistors located in the display region, the pixel driving layer comprising a plurality of gate lines arranged along a first direction, a plurality of data lines arranged along a second direction, and the first thin film transistors located at a region defined by the gate lines and the data lines; forming a gate driving circuit by using the thin film transistors located in the function region.

3 . The method for fabricating an array substrate according to claim 2 , wherein
the thin film transistors located in the display region comprise at least one first thin film transistor, and the thin film transistors in the gate driving circuit comprise at least one second thin film transistor.

4 . The method for fabricating an array substrate according to claim 1 , wherein forming the plurality of first thin film transistors and the plurality of second thin film transistors comprises:
forming a plurality of first gate electrodes and a plurality of second gate electrodes on the first substrate; forming a gate insulating layer on the first gate electrodes and the second gate electrodes; forming a plurality of first oxide semiconductor layers on the gate insulating layer opposite to the first substrate corresponding to a position of the first gate electrodes, and forming a plurality of second oxide semiconductor layers on the gate insulating layer opposite to the first substrate corresponding to a position of the second gate electrodes; forming a first etch stopper layer on the first oxide semiconductor layers, the first etch stopper layer partially covering the first oxide semiconductor layers; forming a second etch stopper layer on the first oxide semiconductor layers covered by the first etch stopper layer and on the second oxide semiconductor layers; and forming source electrodes, drain electrodes and passivation layers of the first thin film transistor and the second thin film transistors.

5 . The method for fabricating an array substrate according to claim 4 , wherein a material of the first etch stopper layer is different from a material of the second etch stopper layer, and/or a thickness of the first etch stopper layer is different from a thickness of the second etch stopper layer.

6 . The method for fabricating an array substrate according to claim 5 , wherein the thickness of the second etch stopper layer is approximately 20 nm-400 nm including the endpoint values, and a thickness difference between the etch stopper layer of the first thin film transistor and the etch stopper layer of the second thin film transistor is approximately 10 nm-300 nm including the endpoint values.

7 . The method for fabricating an array substrate according to claim 4 , after forming the first etch stopper layer on the first oxide semiconductor layers, and before forming the second etch stopper layer on the second oxide semiconductor layers, further comprising:
performing a surface plasma treatment to the second oxide semiconductor layers.

8 . The method for fabricating an array substrate according to claim 7 , wherein the first etch stopper layer and the second etch stopper layer are formed by a same process or by different processes.

9 . The method for fabricating an array substrate according to claim 8 , wherein a film-forming power of the first etch stopper layer is lower than a film-forming power of the second etch stopper layer, or a film-forming temperature of the first etch stopper layer is higher than a film-forming temperature of the second etch stopper layer, or a film-forming pressure of the first etch stopper layer is lower than a film-forming pressure of the second etch stopper layer, or when the first and second etch stopper layers are silicon dioxide, a silane flow of a film-forming process of the first etch stopper layer is higher than a silane flow of a film-forming process of the second etch stopper layer.

10 . An array substrate, comprising:
a first substrate; and a plurality of first thin film transistors and a plurality of second thin film transistors located on the first substrate, wherein an etch stopper layer of the second thin film transistor is different from an etch stopper layer of the first thin film transistors, and a threshold voltage of the second thin film transistors is higher than a threshold voltage of the first thin film transistors.

11 . The array substrate according to claim 10 , wherein the first substrate comprises a display region and a function region, the first substrate further comprising:
a pixel driving layer located in the display region, and a gate driving circuit located in the function region, wherein the pixel driving layer is formed by using the thin film transistors located in the display region, the pixel driving layer comprises a plurality of gate lines arranged along a first direction, a plurality of data lines arranged along a second direction, and the first thin film transistors located at a region defined by the gate lines and the data lines; and the gate driving circuit is formed by using the thin film transistors located in the function region.

12 . The array substrate according to claim 11 , wherein
the thin film transistors located in the display region comprise at least one first thin film transistor; and the thin film transistors in the gate driving circuit comprise at least one second thin film transistor.

13 . The array substrate according to claim 10 , wherein the first thin film transistor comprises:
a first gate electrode located on the first substrate; a gate insulating layer covering the first gate electrode; a plurality of first oxide semiconductor layers located on the gate insulating layer opposite to the first substrate corresponding to a position of the first gate electrodes; a first etch stopper layer located on the first oxide semiconductor layers, the first etch stopper layer partially covering the first oxide semiconductor layers; a second etch stopper layer located on the first oxide semiconductor layers and covered the first etch stopper layer; source electrodes and drain electrodes individually located on two sides of the first etch stopper layer and covering partial of the second etch stopper layer, the source electrodes and the drain electrodes have a projection on the first substrate overlapping at least partial of the first gate electrode; and a passivation layer covering the source electrodes, the drain electrodes, the second etch stopper layer and the gate insulating layer.

14 . The array substrate according to claim 13 , wherein the first etch stopper layer is a silicon oxide layer, a silicon nitride layer or an aluminum oxide layer.

15 . The array substrate according to claim 10 , wherein the second thin film transistor comprises:
a second

Assignees

• Shanghai Tianma Microelectronics Co Ltd
• Tianma Microelectronics Co Ltd

Inventors

• Lou Junhui
• Wu Tianyi

Classifications

• H10P95/70

  Chemical treatments · CPC title

• H10P52/00

  Grinding, lapping or polishing of wafers, substrates or parts of devices · CPC title

• H10P50/20

  Dry etching; Plasma etching; Reactive-ion etching · CPC title

• H01L29/7869

  Electricity · mapped topic

• H01L27/127 Primary

  Electricity · mapped topic