Tft backplate structure and manufacture method thereof

Patent metadata

Field	Value
Publication number	US-2016254282-A1
Application number	US-201414426153-A
Country	US
Kind code	A1
Filing date	Sep 19, 2014
Priority date	Sep 2, 2014
Publication date	Sep 1, 2016
Grant date	—

Abstract

The present invention provides a TFT backplate structure and a manufacture method thereof. The TFT backplate structure comprises a switch TFT (T 1 ) and a drive TFT (T 2 ). The switch TFT (T 1 ) is constructed by a first source/a first drain ( 61 ), a first gate ( 21 ), and a first etching stopper layer ( 51 ), a first semiconductor layer ( 41 ), a first gate isolation layer ( 31 ) sandwiched in between. The drive TFT (T 2 ) is constructed by a second source/a second drain ( 62 ), a second gate ( 22 ), and a second etching stopper layer ( 52 ), a second semiconductor layer ( 42 ), a second gate isolation layer ( 32 ) sandwiched in between. The materials or the thicknesses of the first gate isolation layer ( 31 ) and the second gate isolation layer ( 32 ) are different. Accordingly, the electrical properties of the switch TFT (T 1 ) and the drive TFT (T 2 ) are different.

First claim

What is claimed is:

1 . A TFT backplate structure, comprising a substrate, a first gate and a second gate on the substrate with a distance in between, a first gate isolation layer on the substrate and the first gate, a second gate isolation layer on the substrate and the second gate, a first oxide semiconductor layer right over the first gate and on the first gate isolation layer, a second oxide semiconductor layer right over the second gate and on the second gate isolation layer, a first etching stopper layer on the first oxide semiconductor layer, a second etching stopper layer on the second oxide semiconductor layer, a first source/a first drain on the first gate isolation layer and the first etching stopper layer, a second source/a second drain on the second gate isolation layer and the second etching stopper layer, a protective layer on the first source/the first drain and the second source/the second drain, a pixel electrode on the protective layer; the first source/the first drain are connected to the first oxide semiconductor layer and the second gate, and the second source/the second drain are connected to the second oxide semiconductor layer, the pixel electrode is connected to the second source/the second drain; the first source/the first drain, the first gate, and the first etching stopper layer, the first semiconductor layer, the first gate isolation layer sandwiched in between construct a switch TFT; the second source/the second drain, the second gate, and the second etching stopper layer, the second semiconductor layer, the second gate isolation layer sandwiched in between construct a drive TFT, and structures of the first gate isolation layer and the second gate isolation layer are different, and electrical properties of the switch TFT and the drive TFT are different.

2 . The TFT backplate structure according to claim 1 , wherein material of the first gate isolation layer and material of the second gate isolation layer are different.

3 . The TFT backplate structure according to claim 2 , wherein as material of the first gate isolation layer is SiOx, material of the second gate isolation layer is Al 2 O 3 ;
as material of the first gate isolation layer is SiOx, material of the second gate isolation layer is SiNx; as material of the first gate isolation layer is Al 2 O 3 , material of the second gate isolation layer is mixture of SiNx and SiOx.

4 . The TFT backplate structure according to claim 1 , wherein a thickness of the first gate isolation layer and a thickness of the second gate isolation layer are different.

5 . The TFT backplate structure according to claim 4 , wherein a thickness of the first gate isolation layer is 2000 A, and a thickness of the second gate isolation layer is 4000 A.

6 . A manufacture method of a TFT backplate structure, comprising steps of:
step 1 , providing a substrate, and deposing a first metal film on the substrate, and patterning the first metal film to form a first gate and a second gate with a distance in between; step 2 , forming a first gate isolation layer on the on the substrate and the first gate, and forming a second gate isolation layer on the substrate and the second gate; structures of the first gate isolation layer and the second gate isolation layer are different; step 3 , deposing an oxide semiconductor film on the first, the second gate isolation layers, and patterning the oxide semiconductor film to form a first oxide semiconductor layer, a second oxide semiconductor layer; step 4 , deposing an etching stopper film on the first, the second oxide semiconductor layers and the first, the second gate isolation layers, and patterning the etching stopper film to form a first etching stopper layer, a second etching stopper layer; step 5 , deposing a second metal film on the first, the second etching stopper layers, and the first, the second gate isolation layers, and patterning the second metal film to form a first source/a first drain, and a second source/a second drain; the first source/the first drain are connected to the first oxide semiconductor layer and the second gate, and the second source/the second drain are connected to the second oxide semiconductor layer; step 6 , forming a protective layer on the first source/the first drain, and the second source/the second drain; step 7 , forming a pixel electrode on the protective layer; the pixel electrode is connected to the second source/the second drain.

7 . The manufacture method of the TFT backplate structure according to claim 6 , wherein in the second step, two masks are employed to respectively form the first gate isolation layer and the second gate isolation layer, and material of the first gate isolation layer and material of the second gate isolation layer are different.

8 . The manufacture method of the TFT backplate structure according to claim 7 , wherein as material of the first gate isolation layer is SiOx, material of the second gate isolation layer is Al 2 O 3 ;
as material of the first gate isolation layer is SiOx, material of the second gate isolation layer is SiNx; as material of the first gate isolation layer is Al 2 O 3 , material of the second gate isolation layer is mixture of SiNx and SiOx.

9 . The manufacture method of the TFT backplate structure according to claim 6 , wherein in the second step, a half tone mask is employed to form the first gate isolation layer and the second gate isolation layer, and a thickness of the first gate isolation layer and a thickness of the second gate isolation layer are different.

10 . The manufacture method of the TFT backplate structure according to claim 9 , wherein a thickness of the first gate isolation layer is 2000 A, and a thickness of the second gate isolation layer is 4000 A.

11 . A manufacture method of a TFT backplate structure, comprising steps of:
step 1 , providing a substrate, and deposing a first metal film on the substrate, and patterning the first metal film to form a first gate and a second gate with a distance in between; step 2 , forming a first gate isolation layer on the on the substrate and the first gate, and forming a second gate isolation layer on the substrate and the second gate; structures of the first gate isolation layer and the second gate isolation layer are different; step 3 , deposing an oxide semiconductor film on the first, the second gate isolation layers, and patterning the oxide semiconductor film to form a first oxide semiconductor layer, a second oxide semiconductor layer; step 4 , deposing an etching stopper film on the first, the second oxide semiconductor layers and the first, the second gate isolation layers, and patterning the etching stopper film to form a first etching stopper layer, a second etching stopper layer; step 5 , deposing a second metal film on the first, the second etching stopper layers, and the first, the second gate isolation layers, and patterning the second metal film to form a first source/a first drain, and a second source/a second drain; the first source/the first drain are connected to the first oxide semiconductor layer and the second gate, and the second source/the second drain are connected to the second oxide semiconductor layer; step 6 , forming a protective layer on the first source/the first drain, and the second source/the second drain; step 7 , forming a pixel electrode on the protective layer; the pixel electrode is connected to the second source/the second drain; wherein in the second step, a half tone mask is employed to form the first gate isolation layer and the second gate isolation layer, and a thickness of the first gate isolation layer and a thickness of the second gate isolation layer ar

Assignees

• Shenzhen China Star Optoelect
• Shenzhen China Star Optoelectronics Tech

Inventors

• Lv Xiaowen
• Tseng Chihyuan
• Su Chihyu
• Zhang Hejing

Classifications

• H10D84/01

  Manufacture or treatment · CPC title

• H10D30/6736

  characterised by the shape of gate insulators · CPC title

• H10D86/451

  characterised by the compositions or shapes of the interlayer dielectrics · CPC title

• H10D86/423

  comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO · CPC title

• H10D86/0231

  using masks, e.g. half-tone masks · CPC title