Semiconductor device, method for manufacturing same, and nonvolatile semiconductor memory device
US-9209171-B2 · Dec 8, 2015 · US
Semiconductor device and method of manufacturing semiconductor device
US2017221912A1 · US · A1
| Field | Value |
|---|---|
| Publication number | US-2017221912-A1 |
| Application number | US-201715486338-A |
| Country | US |
| Kind code | A1 |
| Filing date | Apr 13, 2017 |
| Priority date | Nov 14, 2014 |
| Publication date | Aug 3, 2017 |
| Grant date | — |
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- Title
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- Abstract
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Abstract
Official abstract text for this publication.
A method of manufacturing the semiconductor device includes forming a first gate member on a semiconductor substrate through a gate insulating film, forming a spacer on the first gate member, flattening a surface of the spacer, forming a first gate by partially etching the first gate member using the spacer as a mask, forming a second gate member so as to cover the first gate and the spacer having the flattened surface, forming a first insulating film on a surface of the second gate member, and forming a second gate by causing the second gate member to retreat while removing the first insulating film by etching, and the corresponding semiconductor device.
First claim
Opening claim text (preview).
What is claimed is: 1 . A semiconductor device comprising: a semiconductor substrate; a first gate that is provided on the semiconductor substrate through a gate insulating film; a spacer that is provided on the first gate and has a flattened surface; a second gate that is provided on the semiconductor substrate and adjacent to the first gate and the spacer; a source and a drain that are provided at positions between which the first gate and the second gate are interposed; a source wiring that is electrically connected to the source; and a metal compound layer that is provided on each of an upper surface of the second gate, an upper surface of the source wiring, and an upper surface of the drain. 2 . The semiconductor device according to claim 1 , wherein the flattened surface of the first gate is substantially parallel to the principal plane of the semiconductor substrate.
Assignees
Inventors
Classifications
involving a dielectric removal step · CPC title
using masks for conductive or resistive materials · CPC title
Layouts of interconnections · CPC title
Electricity · mapped topic
- H01L27/11521Primary
Electricity · mapped topic
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Frequently asked questions
Answers are generated from the same data shown on this page.
- What does patent US2017221912A1 cover?
- A method of manufacturing the semiconductor device includes forming a first gate member on a semiconductor substrate through a gate insulating film, forming a spacer on the first gate member, flattening a surface of the spacer, forming a first gate by partially etching the first gate member using the spacer as a mask, forming a second gate member so as to cover the first gate and the spacer hav…
- Who is the assignee on this patent?
- Lapis Semiconductor Co Ltd
- What technology area does this patent fall under?
- Primary CPC classification H01L27/11521. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Thu Aug 03 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).