Method of Double Patterning Lithography Process Using Plurality of Mandrels for Integrated Circuit Applications

US2017221702A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2017221702-A1
Application numberUS-201715489037-A
CountryUS
Kind codeA1
Filing dateApr 17, 2017
Priority dateNov 22, 2013
Publication dateAug 3, 2017
Grant date

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  1. Title

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  2. Abstract

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  5. First independent claim

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Abstract

Official abstract text for this publication.

A method includes performing a double patterning process to form a first mandrel, a second mandrel, and a third mandrel, with the third mandrel being between the first mandrel and the second mandrel, and etching the third mandrel to cut the third mandrel into a fourth mandrel and a fifth mandrel, with an opening separating the fourth mandrel from the fifth mandrel. A spacer layer is formed on sidewalls of the first, the second, the fourth, and the fifth mandrels, wherein the opening is fully filled by the spacer layer. Horizontal portions of the spacer layer are removed, with vertical portions of the spacer layer remaining un-removed. A target layer is etched using the first, the second, the fourth, and the fifth mandrels and the vertical portions of the spacer layer as an etching mask, with trenches formed in the target layer. The trenches are filled with a filling material.

First claim

Opening claim text (preview).

What is claimed is: 1 . A method comprising: forming mandrels comprising a first mandrel strip, wherein the first mandrel strip comprises a first portion and a second portion separated from each other by a first opening; depositing a blanket spacer layer over the first mandrel strip; etching horizontal portions of the blanket spacer layer to form spacers, wherein the first opening is filled by a portion of the spacers; etching the first portion and the second portion of the first mandrel strip to form a second opening and a third opening encircled by the mandrels and the spacers; and using the mandrels and the spacers as an etching mask to etch a target layer, with trenches formed in the target layer. 2 . The method of claim 1 further comprising filling the trenches with a metallic material to form conductive lines. 3 . The method of claim 2 , wherein the target layer comprises a dielectric material, and wherein the filling the trenches comprises filling a metallic material. 4 . The method of claim 1 , wherein after the spacers are formed, the spacers further encircle a fourth opening and a fifth opening, and wherein the fourth opening and the fifth opening are on opposite sides of the first opening that is filled by the spacers. 5 . The method of claim 4 , wherein during the etching, portions of the target layer directly underlying the second opening, the third opening, the fourth opening, and the fifth opening are etched. 6 . The method of claim 1 , wherein the forming the first mandrel strip comprises: forming a blanket mandrel layer over the target layer; performing a first etching to remove some portions of the blanket mandrel layer; and performing a second etching on remaining portions of the blanket mandrel layer to form the mandrels comprising the first mandrel strip. 7 . The method of claim 6 , wherein after the first etching, the remaining portions of the blanket mandrel layer comprise: a second mandrel strip and a third mandrel strip parallel to each other; and a fourth mandrel strip and a fifth mandrel strip parallel to each other, wherein the second, the third, the fourth, and the fifth mandrel strips form a rectangular pattern, and the first mandrel strip connects the second mandrel strip to the third mandrel strip. 8 . The method of claim 1 further comprising removing both the first mandrel strip and the spacers. 9 . The method of claim 1 , wherein the mandrels are formed of amorphous silicon. 10 . A method comprising: forming a mandrel layer over a target layer; patterning the mandrel layer to form a mandrel strip comprising a first portion and a second portion having lengthwise directions aligned to a straight line, with an first opening separating the first portion and the second portion from each other; forming spacers to fill the first opening, wherein the spacers comprises portions on opposite sides of the first portion and the second portion of the mandrel strip; partially removing each of the first portion and the second portion of the mandrel strip to form a second opening and a third opening, respectively; and extending the second opening and the third opening into the target layer, wherein in the extending, the spacers and remaining portions of the mandrel layer in combination are used as an etching mask for etching the target layer. 11 . The method of claim 10 , wherein the portions of the spacers further encircle a first and a second strip-shaped opening having lengthwise directions parallel to the lengthwise directions of the mandrel strip. 12 . The method of claim 10 further comprising, after the second opening and the third opening are extended into the target layer, filling the second opening and the third opening with a material different from the target layer. 13 . The method of claim 10 further comprising removing the spacers and the remaining portions of the mandrel layer. 14 . The method of claim 10 , wherein the forming the spacers comprises: forming a blanket spacer layer to fill the first opening; and performing an anisotropic etching on the blanket spacer layer, wherein portions of the blanket spacer layer remaining after the anisotropic etching are the spacers. 15 . A method comprising: forming a mandrel layer over a target layer; performing lithography-and-etching processes to pattern the mandrel layer, with remaining portions of the mandrel layer comprising a first mandrel; etching the first mandrel to cut the first mandrel into a second mandrel and a third mandrel, with a first opening separating the second mandrel from the third mandrel; and depositing a blanket spacer layer over the second mandrel and the third mandrel. 16 . The method of claim 15 further comprising performing an anisotropic etch on the blanket spacer layer, wherein the first opening is fully filled by a remaining portion of the blanket spacer layer, and additional remaining portions of the blanket spacer layer encircle a second opening and a third opening on opposite sides of the first opening. 17 . The method of claim 16 further comprising etching a portion of each of the second mandrel and the third mandrel to form a fourth opening and a fifth opening, respectively, wherein the fourth opening and the fifth opening are located between the second opening and the third opening. 18 . The method of claim 17 further comprising: extending the second opening, the third opening, the fourth opening, and the fifth opening into an underlying target layer; and filling the second opening, the third opening, the fourth opening, and the fifth opening with a filling material. 19 . The method of claim 15 , wherein the forming the mandrel layer comprises forming an amorphous silicon layer. 20 . The method of claim 15 , wherein after the second mandrel and the third mandrel are formed, an I-shaped opening is defined by the remaining portions of the mandrel layer, and the first opening is a part of the I-shaped opening.

Assignees

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Classifications

  • characterised by the processes involved to create the masks · CPC title

  • using masks for insulating materials · CPC title

  • between stacked chips · CPC title

  • characterised by the structures of the outermost layers, e.g. multilayered coatings · CPC title

  • characterised by the structures of the outermost layers, e.g. multilayered coatings · CPC title

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What does patent US2017221702A1 cover?
A method includes performing a double patterning process to form a first mandrel, a second mandrel, and a third mandrel, with the third mandrel being between the first mandrel and the second mandrel, and etching the third mandrel to cut the third mandrel into a fourth mandrel and a fifth mandrel, with an opening separating the fourth mandrel from the fifth mandrel. A spacer layer is formed on s…
Who is the assignee on this patent?
Taiwan Semiconductor Mfg Co Ltd
What technology area does this patent fall under?
Primary CPC classification H10W20/089. Mapped technology areas include Electricity.
When was this patent published?
Publication date Thu Aug 03 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).