Semiconductor devices having a gate structure and a conductive line and methods of manufacturing the same
US-2017200723-A1 · Jul 13, 2017 · US
Memory device and method for fabricating the same
US2017200722A1 · US · A1
| Field | Value |
|---|---|
| Publication number | US-2017200722-A1 |
| Application number | US-201614993099-A |
| Country | US |
| Kind code | A1 |
| Filing date | Jan 12, 2016 |
| Priority date | Jan 12, 2016 |
| Publication date | Jul 13, 2017 |
| Grant date | — |
How to read this patent
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
- Title
What the patent document calls the invention.
- Abstract
A short plain-language summary of the technical disclosure.
- Assignees and inventors
Who owns or filed the patent and who is credited as inventor.
- Key dates
Filing, priority, publication, and grant dates set the timeline.
- First independent claim
The legal scope of protection — read this for what is actually claimed.
- CPC / IPC classifications
Technology tags used to group this patent with similar filings.
- Citations and related patents
Prior art links and similar publications in this corpus.
Abstract
Official abstract text for this publication.
A memory device with a dielectric layer or an air gap between contacts and a method of making the same are disclosed. The method comprises a series of steps including: forming a plurality of conductive lines having trenches therebetween; forming a contact layer in the trench; and forming a dielectric layer interposed in the contact layer and configured to divide the contact layer into two contacts. The method also comprises removing the dielectric layer to form a space and forming a cap layer over the contacts to form an air gap therein. The method further comprises forming a second air gap between the conductive fine and the contact.
First claim
Opening claim text (preview).
1 - 11 . (canceled) 12 . A method for fabricating a memory device, the method comprising: forming a plurality of conductive lines having trenches therebetween; forming a contact layer in the trench; and forming a dielectric layer vertically interposed in the contact layer and configured to divide the contact layer into two contacts. 13 . The method of claim 12 , wherein forming the dielectric layer vertically interposed in the contact layer comprises: forming a hard mask layer over the contact layer and having an opening therein; patterning the contact layer through the opening to form a through hole therein; and filling the through hole with a dielectric material. 14 . The method of claim 12 , further comprising forming an air gap between the contacts. 15 . The method of claim 14 , wherein forming the air gap between the contacts comprises: removing the dielectric layer; and forming a cap layer over the contacts to form the air gap between the contacts. 16 . The method of claim 15 , wherein removing the dielectric layer is performed by dry etching, wet etching, plasma etching, and a combination thereof. 17 . The method of claim 12 , further comprising forming an etch stop layer between the dielectric layer and the contact. 18 . The method of claim 12 , further comprising forming a second air gap between the conductive line and the contact. 19 . The method of claim 18 , wherein forming the second air gap between the conductive line and the contact comprises: forming an oxide layer between the conductive line and the contact; removing the oxide layer; and forming a second cap layer over the conductive line and the contact to form the second air gap between the conductive line and the contact. 20 . The method of claim 19 , further comprising forming a second etch stop layer on sidewalls of the oxide layer.
Assignees
Inventors
Classifications
by filling conductive material into holes, grooves or trenches · CPC title
of conductive parts of the interconnections · CPC title
the openings being via holes penetrating underlying conductors · CPC title
of dielectric parts comprising air gaps · CPC title
comprising air gaps · CPC title
Patent family
Related publications grouped by family.
External sources
Frequently asked questions
Answers are generated from the same data shown on this page.
- What does patent US2017200722A1 cover?
- A memory device with a dielectric layer or an air gap between contacts and a method of making the same are disclosed. The method comprises a series of steps including: forming a plurality of conductive lines having trenches therebetween; forming a contact layer in the trench; and forming a dielectric layer interposed in the contact layer and configured to divide the contact layer into two conta…
- Who is the assignee on this patent?
- Micron Technology Inc
- What technology area does this patent fall under?
- Primary CPC classification H10W20/0698. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Thu Jul 13 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 4 related publications on this page (citations in our corpus or others sharing the same primary CPC).