Semiconductor devices having a gate structure and a conductive line and methods of manufacturing the same

Patent metadata

Field	Value
Publication number	US-2017200723-A1
Application number	US-201615340598-A
Country	US
Kind code	A1
Filing date	Nov 1, 2016
Priority date	Jan 7, 2016
Publication date	Jul 13, 2017
Grant date	—

Abstract

A semiconductor device includes an active pattern. A first source or drain region and a second source or drain region are formed at upper portions of the active pattern. The first source or drain region and the second source or drain region are each disposed adjacent to the gate structure. The gate structure is disposed between the first source or drain region and the second source or drain region. A conductive line is electrically connected to the first source or drain region, the conductive line including a first portion and a second portion. A width of the first portion is greater than a width of the second portion. The width of the first and second portions of the conductive line is measured along a first direction in plan view. A conductive contact is electrically connected to the second source or drain region.

First claim

What is claimed is:

1 . A semiconductor device, comprising:
an active pattern; a gate structure disposed on the active pattern; a first source or drain region and a second source or drain region formed at upper portions of the active pattern, wherein the first source or drain region and the second source or drain region are each disposed adjacent to the gate structure, wherein the gate structure is disposed between the first source or drain region and the second source or drain region; a conductive line electrically connected to the first source or drain region, the conductive line including a first portion and a second portion, wherein a width of the first portion is greater than a width of the second portion, wherein the width of the first and second portions of the conductive line is measured along a first direction in plan view; and a conductive contact electrically connected to the second source or drain region.

2 . The semiconductor device of claim 1 , wherein the first portion of the conductive line overlaps the first source or drain region in plan view.

3 . The semiconductor device of claim 1 , further comprising a plurality of conductive lines and a plurality of active patterns,
wherein at least one of the plurality of conductive lines extends in a second direction that crosses the first direction in plan view, and each of the plurality of conductive lines includes a first portion and a second portion, the first portion being wider than the second portion in the first direction, and wherein at least one of the plurality of active patterns extends along a third direction, the third direction forming an acute angle with respect to the first or second directions, and wherein the plurality of active patterns are spaced apart from each other.

4 . The semiconductor device of claim 3 , wherein a first portion of one of the plurality of conductive lines faces a second portion of another conductive line, of the plurality of conductive lines, in the first direction.

5 . The semiconductor device of claim 3 , wherein each of two neighboring active patterns of the plurality of active patterns includes a second source or drain region, and the second portion of one of the plurality of conductive lines is disposed between the second source or drain regions of the neighboring active patterns.

6 . The semiconductor device of claim 3 , further comprising a plurality of gate structures, wherein at least one of the plurality of gate structures extends in the first direction, and the plurality of the gate structures is arranged along the second direction, wherein at least one of the plurality of gate structures is buried in each of the plurality of active patterns.

7 . The semiconductor device of claim 1 , further comprising a spacer disposed on a sidewall of the conductive line.

8 . The semiconductor device of claim 7 , wherein the conductive contact is in contact with a sidewall of the spacer.

9 . The semiconductor device of claim 1 , further comprising a capacitor or a magnetic tunnel junction (MTJ) structure disposed on the conductive contact.

10 . A semiconductor device, comprising:
a substrate; an isolation layer disposed on the substrate; a plurality of active patterns protruding from the substrate, the active patterns of the plurality of active patterns being spaced apart from each other by the isolation layer; a plurality of gate structures buried in the isolation layer and buried in the active patterns, the plurality of gate structures extending in a first direction parallel to a plane of a top surface of the substrate; first source or drain regions and second source or drain regions formed at upper portions of the plurality of active patterns, the first source or drain regions and the second source or drain regions being separated from each other by the plurality of gate structures; a plurality of conductive lines electrically connected to the first source or drain regions, the plurality of conductive lines extending in a second direction parallel to the top surface of the substrate, wherein the second direction crosses the first direction, and each of the plurality of conductive lines includes enlarged portions and straight portions, wherein the enlarged portions protrude in the first direction and are wider than the straight portions in the first direction; and a plurality of conductive contacts electrically connected to the second source or drain regions of the plurality of active patterns, the plurality of conductive contacts being disposed adjacent to the straight portions of the plurality of conductive lines.

11 . The semiconductor device of claim 10 , wherein the enlarged portions included in different conductive lines of the plurality of conductive lines are arranged in a zigzag configuration in plan view.

12 . The semiconductor device of claim 10 , wherein the plurality of conductive lines are electrically connected to the first source or drain regions using the enlarged portions.

13 . The semiconductor device of claim 10 , wherein the plurality of conductive contacts partially overlap corresponding second source or drain regions in plan view.

14 . The semiconductor device of claim 10 , wherein at least one of the plurality of conductive contacts is interposed between the enlarged portion of a first of the plurality of conductive lines and the linear portion of a second of the plurality of conductive lines.

15 . The semiconductor device of claim 10 , wherein each of the plurality of conductive lines includes a conductive pattern and a mask pattern sequentially stacked on at least one of the plurality of active patterns.

16 . A semiconductor device, comprising:
an active pattern, wherein the active pattern includes a first source or drain region and at least two second source or drain regions, wherein the first source or drain region is disposed between the at least two second source or drain regions; a gate structure disposed on the active pattern, wherein the first source or drain region and one of the at least two second source or drain regions are separated from each other by the gate structure; a conductive line electrically connected to the first source or drain region, wherein the conductive line includes first portions and second portions, the first portions being wider than the second portions in a first direction in plan view, wherein the first and second portions of the conductive line are alternately arranged along a second direction that crosses the first direction in plan view; and a conductive contact electrically connected to one of the at least two second source or drain regions.

17 . The semiconductor device of claim 16 , wherein the first source or drain region is electrically connected to at least one of the first portions of the conductive line.

18 . The semiconductor device of claim 16 , wherein the conductive contact is electrically connected to the one of the at least two second source or drain regions through a portion of the one of the at least two second source or drain regions that does not overlap the conductive contact in plan view.

19 . The semiconductor device of claim 16 , further comprising at least two conductive contacts, wherein one of the second portions of the conductive line is disposed between the at least two conductive contacts.

20 . The semiconductor device of claim 16 , wherein a first insulating interlayer is disposed between the active pattern and the conductive line, and wherein the conductive line and the first s

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Ki-Seok
• Shim Joeong-Seop
• Lee Do-Yeong
• Yoon Chan-Sic

Classifications

• H10W20/43

  Layouts of interconnections · CPC title

• H01L29/0649

  Electricity · mapped topic

• H01L23/528

  Electricity · mapped topic

• H01L27/10814 Primary

  Electricity · mapped topic

• H10D62/115 Primary

  Dielectric isolations, e.g. air gaps · CPC title