Instruction transfer control using program counters

Patent metadata

Field	Value
Publication number	US-2017199741-A1
Application number	US-201614994796-A
Country	US
Kind code	A1
Filing date	Jan 13, 2016
Priority date	Jan 13, 2016
Publication date	Jul 13, 2017
Grant date	—

Abstract

A system that for storing program counter values is disclosed. The system may include a program counter, a first memory including a plurality of sectors, a first circuit configured to retrieve a program instruction from a location in memory dependent upon a value of the program counter, send the value of the program counter to an array for storage and determination a predicted outcome of the program instruction in response to a determination that execution of the program instruction changes a program flow. The second circuit may be configured to retrieve the value of the program counter from a given entry in a particular sector of the array, and determine an actual outcome of the program instruction dependent upon the retrieved value of the program counter.

First claim

What is claimed is:

1 . An apparatus, comprising:
a program counter circuit; a first memory including a plurality of sectors, wherein each sector includes a plurality of entries; a fetch circuit configured to:
retrieve a program instruction from a location in a second memory, wherein the location is dependent upon a value of the program counter circuit;
send the value of the program counter circuit to the first memory for storage in response to a determination that execution of the program instruction changes a program flow; and
determine a predicted outcome of the program instruction in response to the determination that execution of the program instruction changes the program flow; and
wherein the first memory is configured to store the received value of the program counter circuit in a first entry of a first sector; an execution circuit configured to:
retrieve the value of the program counter circuit from the first entry of the first sector of the first memory; and
determine an actual outcome of the program instruction dependent upon the retrieved value of the program counter circuit.

2 . The apparatus of claim 1 , wherein the value of the program counter circuit corresponds to a logical address of the program instruction in the first memory.

3 . The apparatus of claim 1 , wherein to determine the actual outcome of the of the program instruction, the execution circuit is further configured to execute the program instruction.

4 . The apparatus of claim 1 , wherein to determine the actual outcome of the program instruction, the execution circuit is further configured to determine an actual direction and an actual target of the program instruction.

5 . The apparatus of claim 1 , wherein to store the received value of the program counter circuit, the first memory is further configured to allocate a first entry of the plurality of entries of the first sector dependent upon a level of activity of each sector of the plurality of sectors.

6 . The apparatus of claim 5 , wherein the first memory is further configured to allocate, in parallel with allocating the first entry, a second entry of the plurality of entries of a second sector for another value of the program counter circuit corresponding to another program instruction.

7 . A method, comprising:
retrieving, by a fetch circuit of a processor, a program instruction from a location in system memory, wherein the location is dependent upon a value of a program counter circuit; storing the value of the program counter circuit in an array by an array in response to determining that execution of the program instruction changes a program flow; determining, by the fetch unit, a predicted outcome of the program instruction in response to the determining that execution of the program instruction changes the program flow; retrieving, by an execution circuit of a processor, the value of the program counter circuit from the given entry of the particular sector of the first memory; and determining, by the execution circuit, an actual outcome of the of the program instruction dependent upon the retrieved value of the program counter circuit.

8 . The method of claim 7 , wherein the value of the program counter circuit corresponds to a logical address of the program instruction in the first memory

9 . The method of claim 7 , wherein determining, by the execution circuit, the actual outcome of the program instruction includes executing, by the execution circuit, the program instruction.

10 . The method of claim 7 , wherein the array includes a plurality of sectors, and wherein storing the received value of the program counter circuit by an array includes selecting a particular sector of the plurality of sectors, dependent upon a level of activity of each sector of the plurality of sectors.

11 . The method of claim 10 , wherein storing the received value of the program counter circuit includes generating a tag corresponding to a location in the system memory, in which the received value of the program counter circuit is stored.

12 . The method of claim 10 , wherein each sector of the plurality of sectors includes a plurality of entries, and wherein storing the received value of the program counter circuit includes allocating a given entry of the plurality of entries of the particular sector of the plurality of sectors.

13 . The method of claim 10 , further comprising stalling a retrieval of additional program instructions from the memory in response to determining that no entries are available in plurality of entries of each sector of the plurality of sectors to store the received value of the program counter circuit.

14 . A system, comprising:
a memory; and a processor including a storage array and a program counter circuit, wherein the processor is configured to:
retrieve a program instruction from a location in the memory, wherein the location is dependent upon a value of the program counter circuit;
store the value of the program counter circuit to the storage array in response to a determination that the execution of the program instruction changes a program flow; and
determine a predicted outcome of the program instruction in response to the determination that execution of the program instruction changes the program flow;
retrieve the value of the program counter circuit from the storage array; and
determine an actual outcome of the of the program instruction dependent upon the retrieved value of the program counter circuit.

15 . The system of claim 14 , wherein the value of the program counter circuit corresponds to a logical address of the program instruction in the memory.

16 . The system of claim 14 , wherein to determine the actual outcome of the of the program instruction, the processor is further configured to execute the program instruction.

17 . The system of claim 14 , wherein to determine the actual outcome of the conditional, the processor is further configured to determine an actual direction and an actual target of the program instruction.

18 . The system of claim 14 , wherein the storage array includes a plurality of sectors, wherein each sector includes a plurality of entries, and wherein to store the value of the program counter circuit, the processor is further configured to allocate, in parallel, a first entry in a first sector of the plurality of sectors and a second entry in a second sector of the plurality of sectors dependent upon a level of activity of each sector of the plurality of sectors.

19 . The system of claim 18 , wherein the first entry is shared by another program instruction, wherein execution of the another program instruction changes the program flow, and wherein the processor is further configured to de-allocate the first entry in response to a determination that both of the first program instruction and the another program instruction have been executed.

20 . The system of claim 18 , wherein the processor is further configured to stall retrieval of additional program instructions from the memory in response to a determination that no entries are available in plurality of entries of each sector of the plurality of sectors to store the value of the program counter circuit.

Assignees

• Oracle Int Corp

Inventors

• Shah Manish
• Olson Christopher

Classifications

• G06F9/32

  Address formation of the next instruction, e.g. by incrementing the instruction counter (G06F9/38 takes precedence) · CPC title

• G06F9/3005

  to perform operations for flow control · CPC title

• G06F9/3806 Primary

  using address prediction, e.g. return stack, branch history buffer · CPC title

• G06F9/3004

  to perform operations on memory · CPC title

• G06F9/30058 Primary

  Conditional branch instructions · CPC title