Streaming engine with separately selectable element and group duplication
US-11860790-B2 · Jan 2, 2024 · US
Address formation of the next instruction, e.g. by incrementing the instruction counter (G06F9/38 takes precedence)
Address formation of the next instruction, e.g. by incrementing the instruction counter (G06F9/38 takes precedence) · Cooperative Patent Classification (CPC)
Computing, optics, measurement, and control technologies.
Related technology areas
Mapped technology topics for this CPC code.
| Metric | Value |
|---|---|
| CPC code | G06F9/32 |
| Official title | Address formation of the next instruction, e.g. by incrementing the instruction counter (G06F9/38 takes precedence) |
| Display label | Address formation of the next instruction, e.g. by incrementing the instruction counter (G06F9/38 takes precedence) |
| Total patents | 397 |
Filing trend
Year-over-year patent counts classified under this CPC code.
Filing activity over the last five years is declining.
| Year | Patents |
|---|---|
| 2015 | 20 |
| 2016 | 15 |
| 2017 | 51 |
| 2018 | 20 |
| 2019 | 59 |
| 2020 | 41 |
| 2021 | 44 |
| 2022 | 36 |
| 2023 | 26 |
| 2024 | 52 |
| 2025 | 22 |
| 2026 | 11 |
Representative patents
Representative publications under this CPC code from precomputed stats, or recent filings when stats are unavailable.
Method and apparatus for reordering in a non-uniform compute device
US-2017344367-A1 · Nov 30, 2017 · US
Microprocessor using compressed and uncompressed microcode storage
US-9830155-B2 · Nov 28, 2017 · US
Streaming engine with stream metadata saving for context switching
US-2017308381-A1 · Oct 26, 2017 · US
Processor operable to ensure code integrity
US-9798873-B2 · Oct 24, 2017 · US
Instruction prefetching in a computer processor
US-2017269937-A1 · Sep 21, 2017 · US
Implementing a received add program counter immediate shift (addpcis) instruction using a micro-coded or cracked sequence
US-2017249147-A1 · Aug 31, 2017 · US
Dual data streams sharing dual level two cache access ports to maximize bandwidth utilization
US-2017249150-A1 · Aug 31, 2017 · US
Hardware apparatuses and methods to switch shadow stack pointers
US-2017177339-A1 · Jun 22, 2017 · US
Apparatus and method for retrieving elements from a linked structure
US-2017177341-A1 · Jun 22, 2017 · US
Streaming engine with cache-like stream data storage and lifetime tracking
US-2017139710-A1 · May 18, 2017 · US
Method and apparatus for storing event signal and image, and operating method of vision sensor for transmitting event signal to storing apparatus
US-2017127005-A1 · May 4, 2017 · US
Broadcast channel architectures for block-based processors
US-2017083335-A1 · Mar 23, 2017 · US
Implicit program order
US-2017083327-A1 · Mar 23, 2017 · US
Memory synchronization in block-based processors
US-2017083331-A1 · Mar 23, 2017 · US
Prefetching associated with predicated store instructions
US-2017083339-A1 · Mar 23, 2017 · US
Multi-nullification
US-2017083330-A1 · Mar 23, 2017 · US
Distinct system registers for logical processors
US-2017083316-A1 · Mar 23, 2017 · US
Generation and use of block branch metadata
US-2017083319-A1 · Mar 23, 2017 · US
Block-based processor core topology register
US-2017083334-A1 · Mar 23, 2017 · US
Frequently asked questions
Answers are generated from the same data shown on this page.
- What is CPC G06F9/32?
- CPC G06F9/32 is the Cooperative Patent Classification code for “Address formation of the next instruction, e.g. by incrementing the instruction counter (G06F9/38 takes precedence).”
- How many patents are filed under CPC G06F9/32 (Address formation of the next instruction, e.g. by incrementing the instruction counter (G06F9/38 takes precedence))?
- Our database includes 397 publications tagged with this CPC code.
- Is patent activity under CPC G06F9/32 growing?
- Publication counts under this code: 52 in 2024 vs 22 in 2025 (latest complete years).