Boot-strapping systems and techniques for circuits

Patent metadata

Field	Value
Publication number	US-2017194860-A1
Application number	US-201615349691-A
Country	US
Kind code	A1
Filing date	Nov 11, 2016
Priority date	Nov 12, 2015
Publication date	Jul 6, 2017
Grant date	—

Abstract

Boot-strapping systems and techniques for circuits are described. One or more solid-state switches of a switched regulation circuit may be implemented using core transistors and the boot-strapping systems, rather than I/O transistors.

First claim

What is claimed is:

1 . A power conversion circuit comprising:
a supply terminal; a first solid-state switch (M 1 ) having a pair of first switch terminals and a first control terminal, the pair of first switch terminals coupled between the supply terminal and a first node (V A ); a second solid-state switch (M 2 ) having a pair of second switch terminals and a second control terminal, the pair of second switch terminals coupled between the first node (V A ) and a second node (V X ); a third solid-state switch (M 3 ) having a pair of third switch terminals and a third control terminal, the pair of third switch terminals coupled between the second node (V X ) and a third node (V B ); a fourth solid-state switch (M 4 ) having a pair of fourth switch terminals and a fourth control terminal, the pair of fourth switch terminals coupled between the third node (V B ) and a ground terminal (V SS ); an LC circuit including a capacitor coupled between the first node (V A ) and the third node (V B ), and an inductor coupled between the second node (V X ) and a load; and a controller configured to transmit first, second, third, and fourth control signals to control the first, second, third, and fourth solid-state switches through the first, second, third, and fourth control terminals, respectively, to regulate a voltage at the load by repetitively (1) charging the capacitor causing a current to flow in the inductor and (2) discharging the capacitor causing current to flow in the inductor, wherein the first, second, third, and/or fourth solid-state switch comprises one or more core transistors.

2 . The power conversion circuit of claim 1 , wherein the supply terminal is a first supply terminal (V IN ), and wherein the first solid-state switch (M 1 ) comprises:
a first core transistor (M 1 A) having a first pair of diffusion terminals and a first gate terminal (G 1 ), the first pair of diffusion terminals coupled between the first supply terminal (V IN ) and a fourth node (N 1 ); a second core transistor (M 1 B) having a second pair of diffusion terminals and a second gate terminal, the second pair of diffusion terminals coupled between the fourth node and the first node (V A ); a third core transistor (M 11 ) having a third pair of diffusion terminals and a third gate terminal, the third pair of diffusion terminals coupled between the first gate terminal (G 1 ) and the first supply terminal (V IN ); a fourth core transistor (M 12 ) having a fourth pair of diffusion terminals and a fourth gate terminal, the fourth pair of diffusion terminals coupled between the first gate terminal (G 1 ) and the second gate terminal, the fourth gate terminal coupled to the third gate terminal; a circuit component coupling the third and fourth gate terminals to the first control signal; and a second supply terminal (V DD ) coupled to the second gate terminal.

3 . The power conversion circuit of claim 2 , wherein the circuit component includes:
a fifth switch (R 11 ) having a pair of fifth switch terminals and a fifth control terminal, the pair of fifth switch terminals being coupled between the first supply terminal (V IN ) and the third and fourth gate terminals, the fifth control terminal coupled to receive the first control signal; and a sixth switch (R 12 ) having a pair of sixth switch terminals and a sixth control terminal, the pair of sixth switch terminals being coupled between the second supply terminal (V DD ) and the third and fourth gate terminals, the sixth control terminal coupled to receive an inverse of the first control signal.

4 . The power conversion circuit of claim 2 , wherein the circuit component includes a set of one or more inverters coupled in series, an input of the set of inverters coupled to receive the first control signal, an output of the set of inverters coupled to the third and fourth gate terminals.

5 . The power conversion circuit of claim 1 , wherein the supply terminal is a first supply terminal (V IN ), and wherein the second solid-state switch (M 2 ) comprises:
a first core transistor (M 2 A) having a first pair of diffusion terminals and a first gate terminal (G 2 ), the first pair of diffusion terminals coupled between the first node (V A ) and a fourth node (N 2 ); a second core transistor (M 2 B) having a second pair of diffusion terminals and a second gate terminal, the second pair of diffusion terminals coupled between the fourth node and the second node (V X ); a third core transistor (M 21 ) having a third pair of diffusion terminals and a third gate terminal, the third pair of diffusion terminals coupled between the first gate terminal (G 2 ) and the first node (V A ); a fourth core transistor (M 22 ) having a fourth pair of diffusion terminals and a fourth gate terminal, the fourth pair of diffusion terminals coupled between the first gate terminal (G 2 ) and the second gate terminal, the fourth gate terminal coupled to the third gate terminal; a circuit component coupling the third and fourth gate terminals to the second control signal; and a second supply terminal (V DD ) coupled to the second gate terminal.

6 . The power conversion circuit of claim 5 , wherein the circuit component includes:
a fifth switch (R 21 ) having a pair of fifth switch terminals and a fifth control terminal, the pair of fifth switch terminals being coupled between the first node (V A ) and the third and fourth gate terminals, the fifth control terminal coupled to receive an inverse of the second control signal; and a sixth switch (R 22 ) having a pair of sixth switch terminals and a sixth control terminal, the pair of sixth switch terminals being coupled between the second supply terminal (V DD ) and the third and fourth gate terminals, the sixth control terminal coupled to receive the second control signal.

7 . The power conversion circuit of claim 5 , wherein the circuit component includes a set of one or more inverters coupled in series, an input of the set of inverters coupled to receive the second control signal, an output of the set of inverters coupled to the third and fourth gate terminals.

8 . The power conversion circuit of claim 5 , wherein the second solid-state switch further comprises:
a boot capacitor (C B2 ) coupled between the first node (V A ) and the second supply terminal (V DD ); a boot-strapping switch ( 1704 ) having a pair of boot-strapping switch terminals and a boot-strapping switch control terminal, the pair of boot-strapping switch terminals coupled between the second supply terminal (V DD ) and a terminal of the boot capacitor (C B2 ).

9 . The power conversion circuit of claim 8 , further comprising a boot-strapping switch controller ( 1800 b ) having a boot-strapping switch controller output terminal coupled to the boot-strapping switch control terminal, the boot-strapping switch controller configured to provide a boot-strapping control signal on the boot-strapping switch controller output terminal based on the first solid-state switch (M 1 ) being activated.

10 . The power conversion circuit of claim 9 , wherein the boot-strapping control signal comprises a pulse, and wherein the boot-strapping switch controller ( 1800 b ) is configured to provide the pulse with a duration of approximately 2 ns at a time approximately 100 ps after the first solid-state switch (M 1 ) is activated.

11 . The power conversion circuit of claim 9 , wherein the boot-strapping switch controller ( 1800 b ) comprises:
a first delay component ( 1810 ) having a first delay input terminal and a first delay output terminal, the first delay input terminal configured to receive an input signal (M 1 _ON) indicating activation of the first solid-state

Assignees

• Empower Semiconductor Inc

Inventors

• Oak Parag
• Phillips Timothy A

Classifications

• H02M3/158 Primary

  including plural semiconductor devices as final control devices for a single load · CPC title

• H02M1/44

  Circuits or arrangements for compensating for electromagnetic interference in converters or inverters · CPC title

• H02M1/083

  for the ignition at the zero crossing of the voltage or the current · CPC title

• H03K17/04163

  in field-effect transistor switches · CPC title

• H03K17/102

  in field-effect transistor switches · CPC title