Input-output circuits

Patent metadata

Field	Value
Publication number	US-2016149486-A1
Application number	US-201514921192-A
Country	US
Kind code	A1
Filing date	Oct 23, 2015
Priority date	Nov 26, 2014
Publication date	May 26, 2016
Grant date	—

Abstract

A circuit comprises a first circuit and a second circuit. The first circuit is configured to operate at a first-circuit supply voltage value, and to generate a first reference voltage value based on a voltage rated for transistors in a second circuit. The second circuit is configured to operate at a second-circuit supply voltage value, to receive a first signal and the first reference voltage value, and to clamp an input node of the second circuit based on the first reference voltage value. The second-circuit supply voltage value is less than the first-circuit supply voltage value. The first signal is configured to swing between a low voltage value and a voltage value higher than the second-circuit supply voltage value.

First claim

What is claimed is:

1 . A circuit comprising:
a first circuit configured
to operate at a first-circuit supply voltage value; and
to generate a first reference voltage value based on a voltage rated for transistors in a second circuit; and
the second circuit configured
to operate at a second-circuit supply voltage value;
to receive a first signal and the first reference voltage value; and
to clamp an input node of the second circuit based on the first reference voltage value,
wherein
the second-circuit supply voltage value is less than the first-circuit supply voltage value; and
the first signal is configured to swing between a low voltage value and a voltage value higher than the second-circuit supply voltage value.

2 . The circuit of claim 1 , wherein
the second circuit comprises an N-type transistor; a gate of the N-type transistor is configured to have the first reference voltage value; a drain of the N-type transistor is configured to receive the first signal; and a source of the N-type transistor is coupled with the input node of the second circuit.

3 . The circuit of claim 1 , wherein
the first circuit is configured to generate a first voltage value based on the first-circuit supply voltage value; and the first reference voltage value is generated based on the first voltage value.

4 . The circuit of claim 1 , wherein
the first circuit includes at least one diode configured to receive the first-circuit supply voltage value and to generate a first voltage value; and the first reference voltage value is generated based on the first voltage value.

5 . The circuit of claim 4 , comprising
a resistive device having a first end configured to receive the first supply voltage value and a second end configured coupled to the at least one diode and to provide the first voltage value.

6 . The circuit of claim 1 , comprising
an N-type source follower, wherein
a gate of the N-type source follower is configured to receive a first voltage value based on the first-circuit supply voltage value; and
a source of the N-type source follower is configured to provide the first reference voltage value.

7 . The circuit of claim 6 , comprising
a transistor coupled to the N-type source follower and configured as a current path for the N-type source follower.

8 . A circuit comprising:
a first circuit configured
to operate at a first-circuit supply voltage value; and
to generate at least one of a first reference voltage value or a second reference voltage value, based on a voltage rated for transistors in a second circuit; and
the second circuit configured
to operate at the first-circuit supply voltage value;
to receive a first signal and at least one of the first reference voltage value or the second reference voltage value, wherein the first signal is configured to swing between a low voltage value and a high voltage value lower than the first-circuit supply voltage value; and
to keep a voltage across two terminals of a first transistor in the second circuit to be below the voltage rated for the first transistor, based on the at least one of the first reference voltage value or the second voltage value.

9 . The circuit of claim 8 , wherein
the first circuit is configured to generate at least one of a first voltage value or a second voltage value based on the first-circuit supply voltage value; the first reference voltage value is generated based on the first voltage value; and the second reference voltage value is generated based on the second voltage value.

10 . The circuit of claim 8 , wherein
the first circuit includes at least one of
at least one first diode configured to receive the first-circuit supply voltage value and to generate a first voltage value; or
at least one second diode configured to receive the first-circuit supply voltage value and to generate a second voltage value;
the first reference voltage value is generated based on the first voltage value; and the second reference voltage value is generated based on the second voltage value.

11 . The circuit of claim 10 , comprising at least one of
a first resistive device having a first end configured to receive the first-circuit supply voltage value and a second end configured coupled to the at least one first diode and to provide the first voltage value; or a second resistive device having a first end coupled to the at least one second diode and to provide the second voltage value.

12 . The circuit of claim 8 , comprising at least one of
an N-type source follower; or a P-type source follower, wherein
a gate of the N-type source follower is configured to receive a first voltage value based on the first-circuit supply voltage value;
a source of the N-type source follower is configured to provide the first reference voltage value;
a gate of the P-type source follower is configured to receive a second voltage value based on the first-circuit supply voltage value; and
a source of the P-type source follower is configured to provide the second reference voltage value.

13 . The circuit of claim 12 , comprising at least one of
a first transistor; or a second transistor, wherein
the first transistor is coupled to the N-type source follower and configured as a current path for the N-type source follower; and
the second transistor is coupled to the P-type source follower and configured as a current path for the P-type source follower.

14 . The circuit of claim 8 , wherein
the second circuit comprises
a first P-type transistor having a first P-gate, a first P-drain, and a first P-source;
a second P-type transistor having a second P-gate, a second P-drain, and a second P-source;
a first N-type transistor having a first N-gate, a first N-drain, and a first N-source; and
a second N-type transistor having a second N-gate, a second N-drain, and a second N-source;
the first P-source is configured to receive the first-circuit supply voltage value; the first P-drain is coupled with the second P-source; the second P-gate is configured to receive the second reference voltage value; the second P-drain is coupled with the second N-drain; the second N-gate is configured to receive the first reference voltage value; the second N-source is coupled with the first N-drain; the first N-gate is configured to receive a first signal that is configured to swing between a low voltage value and the first-circuit supply voltage value; and the first reference voltage value is clamped based on a voltage rated for the first P-type transistor, and the second voltage value is clamped based on a voltage rated for the first N-type transistor.

15 . The circuit of claim 14 , comprising
a buffer circuit coupled to the first P-drain and a gate of a third P-type transistor.

16 . The circuit of claim 14 , comprising
a buffer circuit configured to buffer a signal at the first P-drain.

17 . A method comprising:
generating a first voltage value based on a first-circuit supply voltage value; generating a first reference voltage value based on a P-type source follower and the first voltage value; applying an input voltage value to a drain of an N-type transistor; and applying the first reference voltage value to a gate of the N-type transistor to clamp a voltage at the source of the N-type transistor based on the input voltage value, the first reference voltage value, and a threshold voltage value of the N-type transistor.

18 . The method of claim 17 , wherein
the source of the N-type transistor

Assignees

• Taiwan Semiconductor Mfg

Inventors

• Roth Alan
• Chang Chia-Chun
• Soenen Eric

Classifications

• H02M3/155 Primary

  using semiconductor devices only · CPC title