High voltage tolerant ldmos

Patent metadata

Field	Value
Publication number	US-2017194487-A1
Application number	US-201615389217-A
Country	US
Kind code	A1
Filing date	Dec 22, 2016
Priority date	Dec 30, 2015
Publication date	Jul 6, 2017
Grant date	—

Abstract

An LDMOS device in FinFET technology is disclosed. In one aspect, the device includes a first region substantially surrounded by a second region of different polarity. The device further includes a first fin in the first region, extending into the second region, the first fin including a doped source region connected with a first local interconnect. The device further includes a second fin in the second region, including a doped drain region connected with a second local interconnect. The device further includes a third fin parallel with the first and second fins including a doped drain region connected with the second local interconnect. The device further includes a gate over the first fin at the border between the first and second regions. A first current path runs over the first and second fins. A second current path runs over and perpendicular to the first fin towards the third fin.

First claim

What is claimed is:

1 . An LDMOS device in FinFET technology, the LDMOS device comprising:
a first region of a first polarity substantially surrounded by a second region of a second polarity wherein the second polarity is opposite to the first polarity; at least one first fin each having a first extremity and a second extremity, wherein each first fin comprises a doped source region in the first region with a polarity opposite to the polarity of the first region; at least one second fin each having a first extremity and a second extremity, the at least one second fin extending in the second region parallel to the at least one first fin, with the first extremities of the at least one second fin being oriented towards the first extremities of the at least one first fin, wherein each second fin comprises a doped drain region with the same polarity as the polarity of the second region; at least one third fin parallel with the at least one first fin and with the at least one second fin, wherein the at least one third fin extends in the second region, each third fin having a first extremity at the level of the second extremities of the at least one first fin and a second extremity at the level of the second extremities of the at least one second fin, wherein each third fin comprises a doped drain region over at least part of its length; a first local interconnect electrically connected with the source regions of the at least one first fin; a second local interconnect electrically connected with the drain regions of the at least one second fin and with the doped drain regions of the at least one third fin; and a gate over the first extremities of the at least one first fin at the border between the first region and the second region, wherein, in operation, a first current path between the first local interconnect and the second local interconnect runs over the at least one first fin and the at least one second fin, and wherein a second current path runs over the at least one first fin and perpendicular from the at least one first fin towards the at least one third fin.

2 . The LDMOS device of claim 1 , further comprising at least two third fins, wherein one of the third fins is on one side of the first and second fins, and wherein another third fin is on the opposite side of the first and second fins.

3 . The LDMOS device of claim 1 , further comprising:
at least two first fins, wherein the source regions of the first fins are connected with the first local interconnect; and at least two second fins wherein the drain regions of the second fins are connected with the second local interconnect.

4 . The LDMOS device of claim 1 , further comprising a doped pick-up region in the first fin, located further away from the second fin than the source region, wherein the polarity of the doped pick-up region is the same as the polarity of the first region.

5 . The LDMOS device of claim 1 , further comprising a doped pick-up region as an extension of the first fin, located further away from the second fin than the source region, wherein the polarity of the doped pick-up region is the same as the polarity of the first region.

6 . The LDMOS device of claim 1 , further comprising at least one pick-up fin in the first region, doped with dopants of the same polarity type as the first region, wherein the first local interconnect connects the source regions of the at least one first fin with the doped region in the at least one pick-up fin.

7 . The LDMOS device of claim 6 , wherein the pick-up fins are alternatingly positioned with the first fins.

8 . The LDMOS device of claim 1 , further comprising at least one additional fin in the second region, each having a first and a second extremity, wherein the at least one additional fin is parallel with the at least one second fin and is located with its first extremity at the level of the first extremity of the at least one second fin and with its second extremity at the level of the second extremity of the at least one second fin, wherein the at least one additional fin is doped with dopants of a polarity type opposite to the polarity of the second region, and wherein the second local interconnect interconnects the at least one additional fin with the at least one second fin.

9 . The LDMOS device of claim 1 , further comprising at least one additional fin in the second region, each having a first and a second extremity, wherein the additional fin is parallel with the at least one first fin and is located with its first extremity at the level of the first extremity of the at least one first fin and with its second extremity at the level of the second extremity of the at least one first fin, and wherein the at least one additional fin is doped with dopants of a polarity type opposite to the polarity of the second region.

10 . The LDMOS device of claim 1 , further comprising a well slot in the second region in between the first fins and the second fins.

11 . The LDMOS device of claim 10 , further comprising a doped pick-up fin above the well slot, the polarity of the pick-up fin being opposite to the polarity of the second region.

12 . The LDMOS device of claim 1 , further comprising shallow trench isolation (STI) regions.

13 . The LDMOS device of claim 12 , wherein the STI regions are formed between the first fins.

14 . The LDMOS device of claim 12 , wherein the STI regions are formed between the second fins.

15 . The LDMOS device of claim 12 , wherein the STI regions are formed between the first fins and the third fins.

16 . The LDMOS device of claim 12 , wherein the STI regions are formed between the second fins and the third fins.

17 . The LDMOS device of claim 12 , wherein the STI regions are formed at the outer side of the third fins opposite to the first fins and second fins.

18 . The LDMOS device of claim 12 , wherein the STI regions are formed in the second region between the at least one first fin and the at least one second fin.

Assignees

• Imec Vzw

Inventors

• Chen Shih-Hung
• Linten Dimitri
• Hellings Geert

Classifications

• H01L29/0649

  Electricity · mapped topic

• H01L29/0869

  Electricity · mapped topic

• H01L29/7851

  Electricity · mapped topic

• H01L29/7816 Primary

  Electricity · mapped topic

• H01L29/0886

  Electricity · mapped topic