Growth of cubic crystalline phase structure on silicon substrates and devices comprising the cubic crystalline phase structure

Patent metadata

Field	Value
Publication number	US-2017194476-A1
Application number	US-201715466461-A
Country	US
Kind code	A1
Filing date	Mar 22, 2017
Priority date	May 4, 2012
Publication date	Jul 6, 2017
Grant date	—

Abstract

A transistor comprises a substrate comprising a Group III/V compound semiconductor material having a cubic crystalline phase structure positioned on a hexagonal crystalline phase layer having a first region and a second region, the cubic crystalline phase structure being positioned between the first region and the second region of the hexagonal crystalline phase layer. A source region and a drain region are both positioned in the Group III/V compound semiconductor material. A channel region is in the Group III/V compound semiconductor material. A gate is over the channel region. An optional backside contact can also be formed. A source contact and electrode are positioned to provide electrical contact to the source region. A drain contact and electrode are positioned to provide electrical contact to the drain region. Methods of forming transistors are also disclosed.

First claim

What is claimed is:

1 . A method of forming a transistor, the method comprising:
providing a substrate comprising a first material portion and a single crystalline silicon layer on the first material portion, the substrate further comprising a major front surface, a major backside surface opposing the major front surface, and a plurality of grooves positioned in the major front surface exposing {111} faces of the single crystalline silicon layer; depositing a buffer layer in one or more of the plurality of grooves; epitaxially growing a semiconductor material over the buffer layer and in the one or more plurality of grooves, the epitaxially grown semiconductor material comprising a hexagonal crystalline phase layer and a cubic crystalline phase structure disposed over the hexagonal crystalline phase layer, one or both of the hexagonal crystalline phase layer and the cubic crystalline phase structure optionally being doped; forming a gate over the cubic crystalline phase structure, the gate comprising an optional gate dielectric and a gate electrode; and forming a source contact and electrode and a drain contact and electrode on the semiconductor material.

2 . The method of claim 1 , further comprising depositing an insulating layer on the major front surface of the substrate prior to depositing the buffer layer, patterning the insulating layer to expose stripes along <011> directions of the substrate, and forming the plurality of grooves in the exposed substrate regions, thereby exposing the {111} faces of the single crystalline silicon layer.

3 . The method of claim 1 , wherein one or more of the plurality of grooves are truncated v-grooves, each truncated v-groove comprising a first diagonal sidewall, a second diagonal sidewall opposing the first diagonal sidewall, and a bottom portion that is parallel with the major front surface of the substrate.

4 . The method of claim 3 , wherein during the epitaxially growing of the semiconductor material a gap is formed between the hexagonal crystalline phase layers and the bottom portion of the truncated v-groove.

5 . The method of claim 1 , further comprising removing at least a portion of the substrate and optionally removing at least a portion of the hexagonal crystalline phase layer.

6 . The method of claim 5 , wherein removing at least a portion of the substrate comprises removing the single crystalline silicon layer.

7 . The method of claim 6 , wherein the hexagonal crystalline phase layer is not removed, and further wherein the cubic crystalline phase structure has a length dimension, a width dimension and a height dimension, the width dimension decreasing with the height so that the structure is tapered, the hexagonal crystalline phase layer being adjacent to the tapered structure, the method optionally comprising doping at least one of the hexagonal crystalline phase layer and the cubic crystalline phase structure to form a source region, a drain region and a channel region.

8 . The method of claim 7 , further comprising etching the semiconductor material to expose a portion of the cubic crystalline material, forming a gate oxide over the cubic crystalline material, and forming a gate electrode over the gate oxide to form a MOS transistor, and optionally forming a backside contact.

9 . The method of claim 8 , wherein a depth of material removed from the height dimension of the cubic crystalline material during the etching determines a gate length of the transistor.

10 . The method of claim 1 , wherein epitaxially growing the semiconductor material comprises forming a heterojunction between the hexagonal crystalline phase layer and the cubic crystalline phase structure, the gate electrode being formed on the cubic crystalline phase structure to form a HEMT (“high-electron-mobility transistor”).

11 . The method of claim 1 , wherein epitaxially growing the semiconductor material comprises forming a heterojunction in the cubic crystalline phase structure, the gate electrode being formed on the cubic crystalline phase structure to form a HEMT (“high-electron-mobility transistor”).

12 . A transistor comprising:
a substrate comprising a Group III/V compound semiconductor material having a cubic crystalline phase structure positioned on a hexagonal crystalline phase layer having a first region and a second region, the cubic crystalline phase structure being positioned between the first region and the second region of the hexagonal crystalline phase layer; a source region and a drain region, both the source region and the drain region positioned in the Group III/V compound semiconductor material; a channel region in the Group III/V compound semiconductor material; a gate over the channel region; an optional backside contact; and a source contact and electrode and a drain contact and electrode, the source contact and electrode positioned to provide electrical contact to the source region and the drain contact and electrode positioned to provide electrical contact to the drain region.

13 . The transistor of claim 12 , wherein:
the source region is in the first region of the hexagonal crystalline phase layer and the drain region is in the second region of the hexagonal crystalline phase layer; the channel region is in the cubic crystalline phase region; and the gate comprises a gate dielectric positioned over the channel region and a gate electrode positioned over the gate dielectric, wherein the cubic crystalline phase structure has a length dimension, a width dimension and a height dimension, the width dimension corresponding to a gate length of the transistor, a portion of the cubic crystalline phase structure being tapered so that the gate length of the transistor can be controlled by controlling the height dimension.

14 . The transistor of claim 13 , wherein the Group III/V compound semiconductor material is a Group III-nitride.

15 . The transistor of claim 13 , wherein the channel region comprises a heterojunction at an interface between the hexagonal crystalline phase layer and the cubic crystalline phase structure, the transistor being a HEMT (“high-electron-mobility transistor”).

16 . The transistor of claim 13 , wherein the channel region comprises a heterojunction in the cubic crystalline phase structure and the transistor is a HEMT.

17 . A device comprising a plurality of transistors of claim 13 , wherein a first one of the transistors has a cubic crystalline phase structure with a first height, and a second one of the transistors has a cubic crystalline phase structure with a second height that is less than the first height, the gate length of the second transistor being greater than the gate length of the first transistor.

18 . A MOSFET transistor comprising:
a substrate comprising a Group III/V compound semiconductor material having a cubic crystalline phase formed in a groove, the groove comprising sidewalls having exposed {111} faces of a crystalline semiconductor; a source region and a drain region in the cubic crystalline phase; a gate dielectric on the cubic crystalline phase between the source region and the drain region; and a gate electrode on the gate dielectric.

19 . The transistor of claim 18 , wherein the Group III/V compound semiconductor material comprising a hexagonal crystalline phase layer epitaxially grown in the groove, the cubic crystalline phase structure epitaxially grown over the hexagonal crystalline phase layer.

Assignees

• Stc Unm

Inventors

• Brueck Steven R J
• Lee Seung-Chang
• Wetzel Christian
• Durniak Mark

Classifications

• H10P95/11

  Separation of active layers from substrates · CPC title

• H10P50/642

  Chemical etching · CPC title

• H10P14/3466

  Crystal orientation · CPC title

• H10P14/3451

  Structure · CPC title

• H10P14/3416

  Nitrides · CPC title