Growth of cubic crystalline phase strucure on silicon substrates and devices comprising the cubic crystalline phase structure

US9520472B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9520472-B2
Application numberUS-201314383833-A
CountryUS
Kind codeB2
Filing dateMar 15, 2013
Priority dateMay 4, 2012
Publication dateDec 13, 2016
Grant dateDec 13, 2016

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Abstract

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A semiconductor device is disclosed. The semiconductor device includes a substrate comprising a groove. A buffer layer is formed on a surface of the groove. The buffer layer comprising at least one material chosen from AIN, GaN or Al x Ga 1-x N, where x is between zero and one. An epitaxially grown semiconductor material is disposed over the buffer layer, at least a portion of the epitaxially grown semiconductor material having a cubic crystalline phase structure. Methods of forming the semiconductor devices are also taught.

First claim

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What is claimed is: 1. A semiconductor device comprising: a (001) crystalline semiconductor substrate comprising a groove exposing (111) faces of crystalline semiconductor; a buffer layer formed on a surface of the groove, the buffer layer comprising at least one material chosen from AlN, GaN or Al x Ga 1-x N, where x is between zero and one; and an epitaxially grown semiconductor material disposed over the buffer layer, the epitaxially grown semiconductor material having a cubic crystalline phase structure and a hexagonal phase structure, wherein the epitaxially grown semiconductor layer includes at least one quantum well spanning and disposed in both the cubic crystalline phase structure and the hexagonal phase structure. 2. The semiconductor device of claim 1 , wherein the groove is a v-groove. 3. The semiconductor device of claim 2 , wherein the width of the v-groove is less than about 10 micrometers. 4. The semiconductor device of claim 1 , wherein the substrate comprises (001) single crystal silicon. 5. The semiconductor device of claim 1 , wherein the buffer layer comprises an AlN nucleation layer and an Al x Ga 1-x N interlayer deposited on the nucleation layer, where x is defined as in claim 1 . 6. The semiconductor device of claim 5 , wherein a concentration of Al and Ga in the interlayer is graded through at least a portion of the thickness of the interlayer. 7. The semiconductor device of claim 5 , wherein a concentration of Al and Ga in the interlayer is substantially constant through the thickness of the interlayer. 8. The semiconductor device of claim 5 , wherein a concentration of Al and Ga varies in a stepwise manner through at least a portion of the thickness of the interlayer. 9. The semiconductor device of claim 1 , wherein the epitaxially grown semiconductor material includes a spatially continuous, phase-separated cubic Ill-nitride material along the length of the groove. 10. The semiconductor device of claim 1 , wherein the epitaxially grown semiconductor material further comprises c-In y Ga 1-y N, where y is greater than zero and equal to or less than one. 11. The semiconductor device of claim 1 , wherein the epitaxially grown semiconductor material includes at least one quantum well. 12. The semiconductor device of claim 1 , wherein the substrate comprises a plurality of grooves and the epitaxially grown semiconductor material comprises a plurality of separated cubic regions formed in the grooves. 13. The semiconductor device of claim 1 , wherein the epitaxially grown semiconductor material comprises a c-GaN region and a h-GaN region. 14. The semiconductor device of claim 1 , wherein the device is an LED, a transistor, a photodetector or a laser. 15. The semiconductor device of claim 1 , wherein the semiconductor device comprises stripes of the epitaxially grown layer and silicon regions, wherein electronic devices are positioned in both the epitaxially grown layer and the silicon regions. 16. A method of forming a semiconductor device, the method comprising: providing a planar crystalline substrate comprising a groove exposing different crystal faces than the planar surface; depositing a buffer layer over the substrate, the buffer layer comprising at least one material chosen from AlN, GaN or Al x Ga 1-x N, where x is between zero and one; epitaxially growing a semiconductor layer over the buffer layer, the epitaxially grown semiconductor layer having a cubic crystalline phase structure and a hexagonal phase structure, wherein the epitaxially grown semiconductor layer includes at least one quantum well spanning and disposed in both the cubic crystalline phase structure and the hexagonal phase structure. 17. The method of claim 16 , further comprising removing at least a portion of the substrate and bonding the remaining portion comprising the epitaxially grown layer to a second substrate. 18. The method of claim 16 , wherein selective area decomposition of a precursor gas is used to form electrical connections to the cubic crystalline devices. 19. The method of claim 16 , wherein the method comprises completely or partially removing at least one of Si material from the substrate, or h-GaN or h-InGaN quantum wells from the epitaxially grown layer. 20. A method of forming a semiconductor device, the method comprising: providing a planar crystalline substrate comprising a groove exposing different crystal faces than the planar surface; depositing a buffer layer over the substrate, the buffer layer comprising at least one material chosen from MN, GaN or Al x Ga 1-x N, where x is between zero and one; epitaxially growing a semiconductor layer over the buffer layer, the epitaxially grown semiconductor layer having a cubic crystalline phase structure and a hexagonal phase structure, wherein the epitaxially grown semiconductor layer includes at least one quantum well spanning both the cubic crystalline phase structure and the hexagonal phase structure; providing a handle wafer; bonding the epitaxially grown semiconductor layer to the handle wafer; removing the substrate; and removing the hexagonal phase structure from the cubic crystalline phase structure.

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What does patent US9520472B2 cover?
A semiconductor device is disclosed. The semiconductor device includes a substrate comprising a groove. A buffer layer is formed on a surface of the groove. The buffer layer comprising at least one material chosen from AIN, GaN or Al x Ga 1-x N, where x is between zero and one. An epitaxially grown semiconductor material is disposed over the buffer layer, at least a portion of the epitaxially g…
Who is the assignee on this patent?
Stc Unm
What technology area does this patent fall under?
Primary CPC classification H10P14/2905. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Dec 13 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).