NiPt AND Ti INTERSECTING SILICIDE PROCESS AND STRUCTURE

Patent metadata

Field	Value
Publication number	US-2017194454-A1
Application number	US-201614988902-A
Country	US
Kind code	A1
Filing date	Jan 6, 2016
Priority date	Jan 6, 2016
Publication date	Jul 6, 2017
Grant date	—

Abstract

A method includes forming a first silicide on a substrate after patterning a gate and spacer onto the substrate. A film is deposited over the substrate. A portion of the dielectric film is removed to expose the first silicide. A portion of the first silicide is removed to form a punch through region. A liner is deposited in the punch through region. A metal layer is deposited on the liner. The substrate is annealed to form a second silicide on the substrate.

First claim

What is claimed is:

1 . A method, comprising:
forming a first silicide on a substrate after patterning a gate and spacer onto the substrate; depositing a dielectric film over the substrate; removing a portion of the dielectric film to expose the first silicide; removing a portion of the first silicide to form a punch through region; depositing a liner in the punch through region; depositing a metal layer on the liner; and annealing the substrate to form a second silicide on the substrate.

2 . The method of claim 1 , further comprising precleaning the substrate and dielectric film before depositing the filler material.

3 . The method of claim 1 , wherein the liner is deposited by plasma vapor deposition ionized plasma vapor deposition, radio frequency plasma vapor deposition, chemical vapor deposition, atomic layer deposition, or a combination comprising at least one of the foregoing.

4 . The method of claim 1 , wherein the metal layer is deposited by plasma vapor deposition ionized plasma vapor deposition, radio frequency plasma vapor deposition, chemical vapor deposition, atomic layer deposition, or a combination comprising at least one of the foregoing.

5 . The method of claim 1 , wherein when annealing, the substrate reacts with the metal layer to form a low resistance silicide.

6 . The method of claim 1 , wherein the annealing is performed at a peak temperature of 400 to 900° C. for 0.1 milliseconds to 30 seconds.

7 . A method, comprising:
forming a first silicide on a substrate after patterning a gate and spacer onto the substrate, wherein the first silicide comprises nickel silicide, nickel platinum silicide, cobalt di-silicide, or a combination comprising at least one of the foregoing; depositing a dielectric film over the substrate; removing a portion of the dielectric film to expose the silicide; removing a portion of the silicide to form a punch through region; depositing a liner in the punch through region, wherein the liner comprises titanium, titanium nitride, or a combination comprising at least one of the foregoing and wherein the liner has a thickness of 4 to 10 nanometers; depositing a metal layer on the liner, wherein the metal layer comprises tungsten; and annealing to form a second silicide on the substrate, wherein the second silicide comprises titanium silicide.

8 . The method of claim 7 , wherein the annealing is performed at a peak temperature of 400 to 900° C. for 0.1 milliseconds to 30 seconds.

9 . A semiconductor device, comprising:
a gate, a spacer, and a substrate, wherein the gate and the spacer are disposed on the substrate; a first silicide on the substrate located between the gate and the spacer; a dielectric film disposed over the substrate; a punch through region in a portion of the dielectric film and the silicide; a liner disposed in the punch region and a metal layer material disposed on the liner; and a second silicide arranged on the substrate underneath the punch through region.

10 . The semiconductor device of claim 9 , wherein the substrate comprises silicon, silicon germanium, silicon carbide, indium gallium arsenide, gallium arsenide, or a combination comprising at least one of the foregoing.

11 . The semiconductor device of claim 9 , wherein the first and/or second silicide materials comprise nickel silicide, nickel platinum silicide, cobalt di-silicide, titanium silicide, titanium nitride silicide, or a combination comprising at least one of the foregoing.

12 . The semiconductor device of claim 9 , wherein the first silicide and/or the second silicide have a thickness of 10 to 25 nanometers.

13 . The semiconductor device of claim 9 , wherein the dielectric film comprises at least one layer.

14 . The semiconductor device of claim 9 , wherein the dielectric film comprises a nitride, an oxide, or a combination comprising at least one of the foregoing.

15 . The semiconductor device of claim 9 , wherein the dielectric film has a thickness of 100 to 800 nanometers.

16 . The semiconductor device of claim 9 , wherein the liner comprises a base portion and an inner portion.

17 . The semiconductor device of claim 16 , wherein the base portion comprises a metal and the inner portion comprises a nitride.

18 . The semiconductor device of claim 16 , wherein the base portion has a thickness of 4 to 10 nanometers and the inner portion has a thickness of 2 to 5 nanometers.

19 . The semiconductor device of claim 9 , wherein the metal layer comprises tungsten.

20 . The semiconductor device of claim 19 , wherein the second silicide comprises a low resistance silicide.

Assignees

• IBM

Inventors

• Breil Nicolas L
• Engel Brett H
• Gribelyuk Michael A
• Ozcan Ahmet S

Classifications

• H10D64/0112

  using conductive layers comprising silicides · CPC title

• H10W20/089

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

• H10W20/047

  by introducing additional elements therein · CPC title

• H10W20/40

  Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title

• H10W20/033

  in openings in dielectrics · CPC title