Silicon nano-tip thin film for flash memory cells

Patent metadata

Field	Value
Publication number	US-2017194445-A1
Application number	US-201715463692-A
Country	US
Kind code	A1
Filing date	Mar 20, 2017
Priority date	Jan 14, 2015
Publication date	Jul 6, 2017
Grant date	—

Abstract

A quantum nano-tip (QNT) thin film, such as a silicon nano-tip (SiNT) thin film, for flash memory cells is provided to increase erase speed. The QNT thin film includes a first dielectric layer and a second dielectric layer arranged over the first dielectric layer. Further, the QNT thin film includes QNTs arranged over the first dielectric layer and extending into the second dielectric layer. A ratio of height to width of the QNTs is greater than 50 percent. A QNT based flash memory cell and a method for manufacture a SiNT based flash memory cell are also provided.

First claim

What is claimed is:

1 . A method for manufacturing a memory cell, the method comprising:
forming a first dielectric layer over a semiconductor substrate; forming a silicon layer over the first dielectric layer; performing a thermal treatment process to crystallize the silicon layer and to grow silicon nano-dots (SiNDs) over the first dielectric layer; exposing the SiNDs to a reactive plasma to shape the SiNDs into silicon nano-tips (SiNTs) having widths tapering away from the first dielectric layer and culminating in points; and forming a second dielectric layer over the first dielectric layer and the SiNTs.

2 . The method according to claim 1 , further including:
forming the SiNTs covering a top surface of the first dielectric layer with a coverage ratio greater than or equal to about 20 percent.

3 . The method according to claim 1 , further including:
forming the SiNTs with a ratio of height to width greater than or equal to about 50 percent.

4 . The method according to claim 1 , further including:
forming the SiNTs with a pyramid or cone shape.

5 . The method according to claim 1 , further including:
forming the first dielectric layer with a thickness of less than about 100 Angstroms; and forming the second dielectric layer with a thickness of less than about 200 Angstroms.

6 . The method according to claim 1 , further including:
forming the first dielectric layer and the second dielectric layer of oxide.

7 . The method according to claim 1 , further including:
forming a control gate over the second dielectric layer; forming a select gate neighboring the control gate; and forming a pair of source/drain regions embedded in a top surface of the semiconductor substrate on opposing sides of the control and select gates.

8 . The method according to claim 7 , further including:
forming the first and second dielectric layers extending between neighboring sidewalls of the control and select gates.

9 . The method according to claim 1 , further including:
forming a storage film over the semiconductor substrate, the storage film comprising the first and second dielectric layers and the SiNTs; forming a control gate layer over the storage film; performing an etch to the semiconductor substrate, through regions of the storage film and the control gate layer overlying a control gate region, to form a control gate stack with a control gate overlying the remaining storage film; forming a spacer layer and a select gate layer stacked in that order over the semiconductor substrate and the control gate stack; and perform a series of one or more etches into the select gate layer to form a select gate neighboring the control gate.

10 . The method according to claim 1 , further including:
forming a select gate dielectric layer and a select gate layer stacked in that order over the semiconductor substrate; performing an etch to the semiconductor substrate, through regions of the select gate dielectric layer and the select gate layer overlying a select gate region, to form a select gate stack with a select gate overlying the remaining select gate dielectric layer; forming a storage film over the semiconductor substrate and the select gate stack, the storage film comprising the first and second dielectric layers and the SiNTs; forming a control gate layer over the storage film; and performing an etch to the semiconductor substrate and the select gate, through regions of the storage film and the control gate layer overlying a control gate region, to form a control gate neighboring the select gate.

11 . A method for manufacturing a memory cell, the method comprising:
forming a first dielectric layer on a semiconductor substrate; forming a silicon layer on the first dielectric layer; performing a thermal treatment process to crystallize the silicon layer and to grow silicon nano-dots (SiNDs) over the first dielectric layer, wherein the SiNDs have a semi-spherical shape; shaping the SiNDs into silicon nano-tips (SiNTs), wherein the SiNTs haves widths decreasing away from the first dielectric layer and culminating in points; forming a second dielectric layer on the first dielectric layer and the SiNTs; and forming a gate electrode covering the second dielectric layer and the SiNTs.

12 . The method according to claim 11 , further including:
forming the SiNTs with a pyramid or cone shape.

13 . The method according to claim 11 , wherein the first and second dielectric layers are formed of silicon dioxide.

14 . The method according to claim 11 , wherein shaping the SiNDs comprises applying a reactive plasma to the SiNDs, and wherein the reactive plasma comprises hydrogen and argon.

15 . The method according to claim 11 , further including:
forming a second gate electrode neighboring the gate electrode; and forming a pair of source/drain regions embedded in a top surface of the semiconductor substrate, wherein the gate electrode and the second gate electrode are spaced between the source/drain regions.

16 . The method according to claim 11 , further including:
forming a gate electrode layer over the second dielectric layer; performing a first etch selectively into the first and second dielectric layers and the gate electrode layer to form the gate electrode, and to further remove portions of the first and second dielectric layers uncovered by the gate electrode; forming a spacer layer covering the gate electrode and lining sidewalls of the gate electrode; forming a second gate electrode layer covering the spacer layer and lining sidewalls of the spacer layer; performing a second etch non-selectively into the gate electrode layer to remove laterally-extending portions of the second gate electrode layer; and performing a third etch selectively into the second gate electrode layer to form a second gate electrode localized to a single side of the gate electrode.

17 . The method according to claim 16 , further including:
performing a fourth etch into the spacer layer with the second gate electrode in place to remove laterally-extending portions of the spacer layer uncovered by the second gate electrode.

18 . The method according to claim 16 , wherein the spacer layer and the second gate electrode layer are formed conformally.

19 . The method according to claim 11 , further including:
before forming the first dielectric layer, forming a second gate electrode, wherein the first dielectric layer is formed covering the second gate electrode and lining sidewalls of the second gate electrode; forming a gate electrode layer covering the second dielectric layer and lining sidewalls of the second dielectric layer; and performing a first etch selectively into the first and second dielectric layers and the gate electrode layer to form the gate electrode, and to further remove portions of the first and second dielectric layers uncovered by the gate electrode, wherein the gate electrode is formed overlapping the second gate electrode.

20 . A method for manufacturing a memory cell, the method comprising:
forming a first gate electrode on a semiconductor substrate; forming a first dielectric layer over the first gate electrode and lining sidewalls of the first gate electrode; forming a silicon layer over the first dielectric layer and lining the first dielectric layer; performing a thermal treatment process to crystallize the silicon layer and to grow silicon nano-dots (SiNDs) on the first dielectric layer, wherein the SiNDs have a semi-spherical pr

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Su Tsu-Hui
• Chen Chih-Ming
• Tsai Chia-Shiung
• Yu Chung-Yi
• Wang Szu-Yu

Classifications

• H10P95/00

  Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass · CPC title

• H10P14/416

  of highly doped semiconductor materials, e.g. polysilicon layers or amorphous silicon layers · CPC title

• H01L21/28273

  Electricity · mapped topic

• H01L29/4916

  Electricity · mapped topic

• H01L29/42332 Primary

  Electricity · mapped topic