Display panel and bi-directional shift register circuit

Patent metadata

Field	Value
Publication number	US-2016104449-A1
Application number	US-201514873683-A
Country	US
Kind code	A1
Filing date	Oct 2, 2015
Priority date	Oct 9, 2014
Publication date	Apr 14, 2016
Grant date	—

Abstract

A display panel includes shift registers coupled in serial. At least one of the shift registers includes an input circuit, an output circuit and a control circuit. The input circuit is coupled to a first input terminal and a second input terminal for respectively receiving a first input signal and a second input signal. The output circuit is coupled to a first clock input terminal for receiving a first clock signal and outputting a pulse signal at an output terminal according to the first clock signal. The control circuit is coupled to the output circuit via a first control node, a second control node and a third control node and controls voltages at the first control node, the second control node and the third control node according to the first input signal or the second input signal, and further controls operations of the output circuit.

First claim

What is claimed is:

1 . A display panel, comprising:
a gate driving circuit, comprising a plurality of shift registers coupled in serial, wherein at least one of the shift registers comprises: an input circuit, coupled to a first input terminal and a second input terminal for respectively receiving a first input signal and a second input signal; an output circuit, coupled to a first clock input terminal for receiving a first clock signal and outputting a pulse signal at an output terminal according to the first clock signal; and a control circuit, coupled to the output circuit via a first control node, a second control node and a third control node and controlling voltages at the first control node, the second control node and the third control node according to the first input signal or the second input signal, and further controlling operations of the output circuit.

2 . The display panel as claimed in claim 1 , wherein the shift register further comprises:
a switch circuit, coupled to a second clock input terminal and a third clock input terminal for receiving a second clock signal and a third clock signal, wherein when the shift register operates in a forward scan, the switch circuit transmits the second clock signal to the control circuit, and when the shift register operates in a reverse scan, the switch circuit transmits the third clock signal to the control circuit.

3 . The display panel as claimed in claim 1 , wherein the control circuit is further coupled to a second clock input terminal and a third clock input terminal for receiving a second clock signal and a third clock signal.

4 . The display panel as claimed in claim 1 , wherein the output circuit comprises:
a first transistor, coupled to the first clock input terminal, the first control node and the output terminal; and a second transistor, coupled to the output terminal, the second control node and a low operation voltage, wherein the first transistor is turned on or off according to the voltage at the first control node and the second transistor is turned on or off according to the voltage at the second control node, and wherein after outputting the pulse signal, a voltage at the output terminal is discharged through the first transistor and the second transistor.

5 . The display panel as claimed in claim 1 , wherein the control circuit comprises:
a third transistor, coupled to a high operation voltage, a fourth control node and the first control node; a fourth transistor, coupled to the high operation voltage, a fifth control node and the second control node; and a fifth transistor, coupled to the high operation voltage, a fourth clock input terminal and the third control node, wherein the third transistor is turned on or off according to a voltage at the fourth control node for controlling the voltage at the first control node, the fourth transistor is turned on or off according to a voltage at the fifth control node for controlling the voltage at the second control node, and the fifth transistor is turned on or off according to a voltage of a fourth clock signal for controlling the voltage at the third control node.

6 . The display panel as claimed in claim 5 , wherein the control circuit further
a sixth transistor, coupled to the first control node, the third control node and a low operation voltage; a seventh transistor, coupled to the second control node, the fourth control node and the low operation voltage; and an eighth transistor, coupled to the third control node, the fourth control node and the low operation voltage, wherein the sixth transistor is turned on or off according to the voltage at the third control node for controlling the voltage at the first control node, the seventh transistor is turned on or off according to a voltage at the fourth control node for controlling the voltage at the second control node and the eighth transistor is turned on or off according to the voltage at the fourth control node for controlling the voltage at the third control node.

7 . The display panel as claimed in claim 3 , wherein the input circuit comprises:
a third transistor, coupled to a high operation voltage, the first input terminal and the first control node, and wherein the control circuit comprises: a fourth transistor, coupled to the high operation voltage, the second clock input terminal and the second control node; and a fifth transistor, coupled to the high operation voltage, a fourth clock input terminal and the third control node, wherein the third transistor is turned on or off according to a voltage of the first input signal for controlling the voltage at the first control node, the fourth transistor is turned on or off according to a voltage of the second clock signal for controlling the voltage at the second control node, and the fifth transistor is turned on or off according to a voltage of a fourth clock signal for controlling the voltage at the third control node.

8 . The display panel as claimed in claim 7 , wherein the control circuit further comprises:
a sixth transistor, coupled to the second control node, the first clock input terminal and the third control node; a seventh transistor, coupled to the first control node, the third control node and a low operation voltage; and an eighth transistor, coupled to the third control node, the first control node and the low operation voltage, wherein the sixth transistor is turned on or off according to a voltage of the first clock signal for controlling the voltage at the second control node, the seventh transistor is turned on or off according to the voltage at the third control node for controlling the voltage at the first control node and the eighth transistor is turned on or off according to the voltage at the first control node for controlling the voltage at the third control node.

9 . The display panel as claimed in claim 8 , wherein the input circuit further comprises:
a ninth transistor, coupled to the high operation voltage, the second input terminal and the first control node, and wherein the control circuit further comprises: a tenth transistor, coupled to the high operation voltage, the third clock input terminal and the second control node.

10 . The display panel as claimed in claim 1 , wherein each shift register receives at least four clock signals, and wherein a rising edge of one of the clock signals closes to a falling edge of another of the clock signals.

11 . The display panel as claimed in claim 4 , wherein a width of the second transistor is greater than a width of the first transistor.

12 . A bi-directional shift register circuit for generating a plurality of gate driving signals and comprising a plurality of shift registers, wherein at least one shift register comprises:
an input circuit, coupled to a first input terminal and a second input terminal for respectively receiving a first input signal and a second input signal; an output circuit, coupled to a first clock input terminal for receiving a first clock signal and outputting a pulse signal at an output terminal according to the first clock signal; a control circuit, coupled to the output circuit via a first control node, a second control node and a third control node and controls voltages at the first control node, the second control node and the third control node according to the first input signal or the second input signal, and further controls operations of the output circuit; a second clock input terminal, receiving a second clock signal; and a third clock input signal, receiving a third clock signal, wherein when the shift register operates in a forward scan, a falling edge of the first clo

Assignees

• Innolux Corp

Inventors

• Huang Sheng-Feng

Classifications

• G09G3/3688 Primary

  suitable for active matrices only · CPC title

• G09G2310/0283

  Arrangement of drivers for different directions of scanning · CPC title

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title

• G09G2340/0492

  Change of orientation of the displayed image, e.g. upside-down, mirrored · CPC title

• G11C19/287

  Organisation of a multiplicity of shift registers · CPC title