Shift register unit, driving method, gate driving circuit and display device

Patent metadata

Field	Value
Publication number	US-2017193885-A1
Application number	US-201615198674-A
Country	US
Kind code	A1
Filing date	Jun 30, 2016
Priority date	Jan 4, 2016
Publication date	Jul 6, 2017
Grant date	—

Abstract

The present disclosure provides a shift register unit, a driving method, a gate driving circuit and a display device. The shift register unit includes a pull-up transistor; a storage capacitor; an output noise reduction transistor; a pull-down node control module, which controls a pull-down node to be at a first low level or a first high level under the control of the pull-up node; a pull-up node control module, which controls the pull-up node to be or not to be at a second high level under the control of an input signal and controls the pull-up node to be at or not to be at a second low level under the control of a reset signal; and a pull-up node noise reduction module, which controls the pull-up node to be or not to be at the first low level under the control of the pull-down node.

First claim

What is claimed is:

1 . A shift register unit, comprising:
a gate driving signal output end; a clock signal input end; an input end, wherein an input signal is capable of being applied to the input end; a reset end, wherein a reset signal is capable of being applied to the reset end; a pull-up transistor, wherein a gate electrode of the pull-up transistor is connected to a pull-up node, a first electrode of the pull-up transistor is connected to the clock signal input end, and a second electrode of the pull-up transistor is connected to the gate driving signal output end; a storage capacitor, wherein a first end of the storage capacitor is connected to the pull-up node, and a first low level is applied to a second end of the storage capacitor; an output noise reduction transistor, wherein a gate electrode of the output noise reduction transistor is connected to a pull-down node, a first electrode of the output noise reduction transistor is connected to the gate driving signal output end, and the first low level is applied to a second electrode of the output noise reduction transistor; a pull-down node control module that is connected to the pull-up node and the pull-down node, and configured to apply the first low level or a first high level to the pull-down node under the control of the pull-up node; a pull-up node control module that is connected to the input end, the reset end, the pull-up node, a second high level and a second low level, and configured to apply or not apply the second high level to the pull-up node under the control of the input signal and apply or not apply the second low level to the pull-up node under the control of the reset signal; and a pull-up node noise reduction module, wherein a control end of the pull-up node noise reduction module is connected to the pull-down node, and configured to apply or not apply the first low level to the pull-up node under the control of the pull-down node.

2 . The shift register unit according to claim 1 , wherein the pull-up node control module comprises a first transistor and a second transistor, wherein
in the case of performing forward scanning, a gate electrode of the first transistor is connected to the input end, the second high level is applied to a first electrode of the first transistor, a second electrode of the first transistor is connected to the pull-up node, a gate electrode of the second transistor is connected to the reset end, a first electrode of the second transistor is connected to the pull-up node, and the second low level is applied to a second electrode of the second transistor; and in the case of performing backward scanning, the gate electrode of the first transistor is connected to the reset end, the second low level is applied to the first electrode of the first transistor, the second electrode of the first transistor is connected to the pull-up node, the gate electrode of the second transistor is connected to the input end, the first electrode of the second transistor is connected to the pull-up node, and the second high level is applied to the second electrode of the second transistor.

3 . The shift register unit according to claim 1 , wherein the pull-up node noise reduction module comprises a pull-up node noise reduction transistor, wherein the gate electrode of the pull-up node noise reduction transistor is connected to the pull-down node, a first electrode of the pull-up node noise reduction transistor is connected to the pull-up node, and the first low level is applied to a second electrode of the pull-up node noise reduction transistor.

4 . The shift register unit according to claim 1 , wherein the pull-down node control module is configured to control the pull-down node to be at the first low level in the case that the pull-up node is at the second high level and control the pull-down node to be at the first high level in the case that the pull-up node is at the second low level.

5 . The shift register unit according to claim 2 , wherein the pull-down node control module is configured to control the pull-down node to be at the first low level in the case that the pull-up node is at the second high level and control the pull-down node to be at the first high level in the case that the pull-up node is at the second low level.

6 . The shift register unit according to claim 3 , wherein the pull-down node control module is configured to control the pull-down node to be at the first low level in the case that the pull-up node is at the second high level and control the pull-down node to be at the first high level in the case that the pull-up node is at the second low level.

7 . The shift register unit according to claim 4 , wherein the pull-down node control module comprises:
a third transistor, wherein the first high level is applied to a gate electrode of the third transistor, the first high level is applied to a first electrode of the third transistor, and a second electrode of the third transistor is connected to the pull-down node; and a fourth transistor, wherein a gate electrode of the fourth transistor is connected to the pull-up node, a first electrode of the fourth transistor is connected to the pull-down node, and the first low level is applied to a second electrode of the fourth transistor.

8 . The shift register unit according to claim 7 , wherein all of the pull-up transistor, the output noise reduction transistor, the pull-up node noise reduction transistor, the first transistor, the second transistor, the third transistor and the fourth transistor are N-type transistors.

9 . A method for driving the shift register unit according to claim 1 , wherein in each display period, the method comprises steps of:
at a pre-charging stage, applying the high level to the input end, applying the low level to the reset end, applying the low level to the clock signal input end, controlling the pull-up node to be at the second high level by the pull-up node control module, charging the storage capacitor, keeping the pull-up node at the high level, controlling the pull-up transistor to be turned on, controlling the pull-down node to be at the first low level by the pull-down node control module, so as to control the output noise reduction transistor to be turned off, and control the gate driving signal output end to output the low level; at an output stage, applying the low level to the input end, applying the low level to the reset end, applying the high level to the clock signal input end, keeping the pull-up node at the high level by the storage capacitor, controlling the pull-up transistor to be turned on, so as to output the high level by the gate driving signal output end, and keeping the pull-down node at the first low level by the pull-down node control module; at a reset stage, applying the low level to the input end, applying the high level to the reset end, applying the low level to the clock signal input end, controlling the pull-up node to be at the second low level by the pull-up node control module, controlling the pull-down node to be at the first high level by the pull-down node control module, controlling the pull-up node to be at the first low level by the pull-up node noise reduction module to perform noise reduction on the pull-up node, and turning on the output noise reduction transistor to perform noise reduction on the gate driving signal output end, so as to apply the first low level to the gate driving signal output end; and at a constant noise reduction stage, applying the low level to the input end, applying the low level to the reset end, controlling the pull-down node to be at the first high level by the pull-down node control module, controlling the pull-up node to be at the first low level by the

Assignees

• Boe Technology Group Co Ltd
• Hefei Boe Optoelectronics Tech

Inventors

• Feng Silin
• Li Hongmin

Classifications

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title

• G11C19/184

  with field-effect transistors, e.g. MOS-FET · CPC title

• G11C19/28 Primary

  using semiconductor elements (G11C19/14, G11C19/36 take precedence) · CPC title

• G09G2310/0267

  Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays · CPC title

• G09G3/20

  for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} · CPC title