Pixel circuit, display panel and display device

Patent metadata

Field	Value
Publication number	US-2017193906-A1
Application number	US-201615226702-A
Country	US
Kind code	A1
Filing date	Aug 2, 2016
Priority date	Jan 5, 2016
Publication date	Jul 6, 2017
Grant date	—

Abstract

Disclosed is a pixel circuit which includes a multiplexing module and a plurality of sub-pixels. Signals for detecting parameters of respective sub-pixels are transferred via a sensing line in a time-divisional manner. For each sub-pixel, connection to the data line and the sensing line is achieved via a common terminal. Further disclosed are a display panel and a display device.

First claim

What is claimed is:

1 . A pixel circuit, comprising:
a multiplexing module having a data terminal connected to a data line, a sensing terminal connected to a sensing line, a data control terminal for receiving a data control signal, a sensing control terminal for receiving a sensing control signal, a plurality of pixel control terminals for receiving respective pixel control signals, and a plurality of common terminals; and a plurality of sub-pixels comprising respective light-emitting devices and respective driving modules for driving the light-emitting devices, each of the light-emitting devices having an input terminal, each of the driving modules being connected to a corresponding one of the common terminals and the input terminal of a corresponding one of the light-emitting devices and having a first scanning terminal connected to a first scanning line and a second scanning terminal connected to a second scanning line; wherein the plurality of pixel control terminals correspond one-to-one with the plurality of sub-pixels, and the plurality of common terminals correspond one-to-one with the plurality of sub-pixels; wherein, in a detection mode for each sub-pixel, the multiplexing module is configured to, in response to the data control signal, the sensing control signal, and the pixel control signal received by one of the plurality of pixel control terminals that corresponds to the sub-pixel, successively transfer a detection reset voltage from the sensing line and a detection voltage from the data line to one of the plurality of common terminals that corresponds to the sub-pixel, and the driving module of the sub-pixel is configured to, in response to the first scanning signal from the first scanning line and the second scanning signal from the second scanning line, reset a voltage at the input terminal of the light-emitting device of the sub-pixel based on the detection reset voltage, cause a change in the voltage at the input terminal of the light-emitting device of the sub-pixel based on the detection voltage, and further transfer the changed voltage to the common terminal corresponding to the sub-pixel for output through the sensing line; and wherein, in a light-emitting mode for each sub-pixel, the multiplexing module is configured to, in response to the data control signal, the sensing control signal, and the pixel control signal received by one of the plurality of pixel control terminals that corresponds to the sub-pixel, successively transfer a light-emitting reset voltage from the sensing line and a data voltage from the data line to one of the plurality of common terminals that corresponds to the sub-pixel, and the driving module of the sub-pixel is configured to, in response to the first scanning signal from the first scanning line and the second scanning signal from the second scanning line, reset a voltage at the input terminal of the light-emitting device of the sub-pixel based on the light-emitting reset voltage, and drive the light-emitting device of the sub-pixel to emit light based on the data voltage.

2 . The pixel circuit according to claim 1 , wherein the multiplexing module comprises a first multiplexing unit and a second multiplexing unit, wherein:
the first multiplexing unit has the data terminal, the sensing terminal, the data control terminal and the sensing control terminal, and is configured to, in response to the data control signal and the sensing control signal, selectively couple one of the data terminal and the sensing terminal to a first node; and the second multiplexing unit has the plurality of pixel control terminals and the plurality of common terminals, and is configured to, in response to the pixel control signals received by the plurality of pixel control terminals, selectively couple the first node to one of the plurality of common terminals.

3 . The pixel circuit according to claim 2 , wherein the second multiplexing unit comprises a first switch unit, a second switch unit and a third switch unit, and wherein the plurality of sub-pixels comprise a first sub-pixel, a second sub-pixel and a third sub-pixel.

4 . The pixel circuit according to claim 3 , wherein the first switch unit comprises a first transistor having a gate connected to one of the plurality of pixel control terminals that corresponds to the first sub-pixel, a first electrode connected to the first node, and a second electrode connected to one of the plurality of common terminals that corresponds to the first sub-pixel.

5 . The pixel circuit according to claim 3 , wherein the second switch unit comprises a second transistor having a gate connected to one of the plurality of pixel control terminals that corresponds to the second sub-pixel, a first electrode connected to the first node, and a second electrode connected to one of the plurality of common terminals that corresponds to the second sub-pixel.

6 . The pixel circuit according to claim 3 , wherein the third switch unit comprises a third transistor having a gate connected to one of the plurality of pixel control terminals that corresponds to the third sub-pixel, a first electrode connected to the first node, and a second electrode connected to one of the plurality of common terminals that corresponds to the third sub-pixel.

7 . The pixel circuit according to claim 2 , wherein the first multiplexing unit comprises:
a fourth transistor having a gate connected to the data control terminal, a first electrode connected to the data terminal, and a second electrode connected to the first node; and a fifth transistor having a gate connected to the sensing control terminal, a first electrode connected to the first node, and a second electrode connected to the sensing terminal.

8 . The pixel circuit according to claim 1 , wherein the driving module of each sub-pixel comprises a reset unit, a driving unit and a write unit, wherein:
the write unit has the first scanning terminal and is connected to a second node and the common terminal corresponding to the sub-pixel, wherein the write unit is configured to, in response to the first scanning signal, couple the common terminal corresponding to the sub-pixel to the second node; the driving unit is connected to the second node, a first power supply voltage and the input terminal of the light-emitting device, wherein the driving unit is configured to, in response to the detection voltage provided to the second node, to cause the change in the voltage at the input terminal of the light-emitting device in the detection mode, and, in response to the data voltage provided to the second node, drive the light-emitting device of the sub-pixel to emit light in the light-emitting mode; and the reset unit has the second scanning terminal and is connected to the input terminal of the light-emitting device and the common terminal corresponding to the sub-pixel, wherein the reset unit is configured to, in the detection mode in response to the second scanning signal, reset the voltage at the input terminal of the light-emitting device based on the detection reset voltage and transfer the changed voltage at the input terminal of the light-emitting device which is caused by application of the detection voltage at the second node to the common terminal corresponding to the sub-pixel, and, in the light-emitting mode in response to the second scanning signal, reset the voltage at the input terminal of the light-emitting device based on the light-emitting reset voltage.

9 . The pixel circuit according to claim 8 , wherein the write unit comprises a sixth transistor having a gate connected to the first scanning terminal, a first electrode connected to the second node, and a second electrode connected to the common terminal corresponding to the sub

Assignees

• Boe Technology Group Co Ltd

Inventors

• Li Yongqian
• Lin Yicheng
• Li Quanhu

Classifications

• G09G3/3233 Primary

  with pixel circuitry controlling the current through the light-emitting element · CPC title

• G09G2300/0426

  Layout of electrodes and connections · CPC title

• G09G3/3258 Primary

  with pixel circuitry controlling the voltage across the light-emitting element · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title

• G09G3/3275 Primary

  Details of drivers for data electrodes · CPC title