Organic light emitting device

US9626906B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9626906-B2
Application numberUS-201414557495-A
CountryUS
Kind codeB2
Filing dateDec 2, 2014
Priority dateDec 20, 2013
Publication dateApr 18, 2017
Grant dateApr 18, 2017

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

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Disclosed is an organic light emitting display in which a sensing period during which the source voltage of the driving TFT is raised toward a data voltage applied to a gate electrode of the driving TFT in order to compensate a change in mobility of the driving TFT, a first gate signal is maintained at an ON level and a second gate signal is maintained at an OFF level, and the first and second gate signals are maintained at an OFF level in a light emission period following the sensing period; and a first falling time of the first gate signal and a second falling time of the second gate signal, which indicate a period of time required to change from the ON level to the OFF level, are set to be longer than a predetermined reference value, respectively.

First claim

Opening claim text (preview).

What is claimed is: 1. An organic light emitting display, comprising: a display panel having a plurality of pixels each including an organic light emitting diode, a driving TFT controlling a driving current flowing through the organic light emitting diode depending on a voltage difference between a gate electrode connected to a first node and a source electrode connected to a second node, a first switch TFT switched in response to a first gate signal to apply a data voltage to the first node, a second switch TFT switched in response to a second gate signal to apply an initialization voltage to the second node, and a storage capacitor connected between the first node and the second node; a data driving circuit supplying the data voltage to a data line connected to the plurality of pixels and supplying the initialization voltage to a reference line connected to the plurality of pixels; and a gate driving circuit supplying the first gate signal to a first gate line connected to the plurality of pixels and supplying the second gate signal to a second gate line connected to the plurality of pixels, wherein, in a sensing period during which differences in mobilities of the driving TFTs are compensated, the first gate signal is maintained at an ON level and the second gate signal is maintained at an OFF level, the first and second gate signals are maintained at an OFF level in a light emission period following the sensing period, and a gate voltage and a source voltage of the driving TFT are raised to a voltage level higher than the threshold voltage of the organic light emitting diode while a gate-source voltage of the driving TFT supplied during the sensing period is maintained, and wherein the differences in the mobilities of the driving TFTs are compensated by setting a first falling time of the first gate signal and a second falling time of the second gate signal after compensation, which indicate periods of time required to respectively change the first gate signal and the second gate signal from the ON level to the OFF level, to be 4-6 times longer than the first falling time of the first gate signal and the second falling time of the second gate signal before compensation. 2. The organic light emitting display of claim 1 , wherein the second falling time is set to be longer than the first falling time. 3. The organic light emitting display of claim 1 , wherein the gate driving circuit includes a first CMOS inverter outputting the first gate signal through a first output node, and a second CMOS inverter outputting the second gate signal through a second output node, wherein the first CMOS inverter includes a first PMOS transistor connected between a high-voltage power of the ON level and the first output node and a first NMOS transistor connected between a low-voltage power of the OFF level and the first output node, wherein the second CMOS inverter includes a second PMOS transistor connected between a high-voltage power of the ON level and the second output node and a second NMOS transistor connected between a low-voltage power of the OFF level and the second output node, and wherein the channel capacities of the first and second NMOS transistors are, respectively, controlled according to the setting of the first and second falling times. 4. The organic light emitting display of claim 1 , wherein a voltage difference between the ON level and the OFF level of the first gate signal is equal to a voltage difference between ON level and the OFF level of the second gate signal, and wherein the ON levels of the first and second gate signals are different from each other, and the OFF levels of the first and second gate signals are different from each other. 5. The organic light emitting display of claim 4 , wherein the ON level of the first gate signal is higher than the ON level of the second gate signal, and the OFF level of the first gate signal is higher than the OFF signal of the second gate signal. 6. The organic light emitting display of claim 1 , wherein, when an RC delay applied to the first and second gate signals is gradually increased from a first region toward a second region of the display panel, the channel capacity of the driving TFT is gradually increased from the first region toward the second region. 7. The organic light emitting display of claim 1 , wherein, when an RC delay applied to the first and second gate signals is gradually increased from a first region toward a second region of the display panel, the capacitance of the storage capacitor is gradually decreased from the first region toward the second region. 8. The organic light emitting display of claims 1 , wherein, when an RC delay applied to the first and second gate signals is gradually increased from a first region toward a second region of the display panel, the channel capacity of the driving TFT is gradually increased from the first region toward the second region, and the capacitance of the storage capacitor is gradually decreased from the first region toward the second region. 9. The organic light emitting display of claim 1 , wherein the ON level is equivalent to 100% of a gate high voltage and the OFF level is equivalent to 10% of the gate high voltage. 10. The organic light emitting display of claim 1 , wherein the differences in mobilities of the driving TFTs are compensated by ±20%. 11. An organic light emitting display, comprising: a display panel having a plurality of pixels each including an organic light emitting diode, a driving TFT controlling a driving current flowing through the organic light emitting diode depending on a voltage difference between a gate electrode connected to a first node and a source electrode connected to a second node, a first switch TFT switched in response to a first gate signal to apply a data voltage to the first node, a second switch TFT switched in response to a second gate signal to apply an initialization voltage to the second node, and a storage capacitor connected between the first node and the second node; a data driving circuit supplying the data voltage to a data line connected to the plurality of pixels and supplying the initialization voltage to a reference line connected to the plurality of pixels; and a gate driving circuit supplying the first gate signal to a first gate line connected to the plurality of pixels and supplying the second gate signal to a second gate line connected to the plurality of pixels, wherein, in a sensing period during which differences in mobilities of the driving TFTs are compensated, the first gate signal is maintained at an ON level and the second gate signal is maintained at an OFF level, and the first and second gate signals are maintained at an OFF level in a light emission period following the sensing period, wherein the differences in the mobilities of the driving TFTs are compensated by setting a first falling time of the first gate signal and a second falling time of the second gate signal after compensation, which indicate periods of time required to respectively change the first gate signal and the second gate signal from the ON level to the OFF level, to be longer than the first falling time of the first gate signal and the second falling time of the second gate signal before compensation, and wherein the second falling time is set to be longer than the first falling time. 12. The organic light emitting display of claim 11 , wherein the ON level is equivalent to 100% of a gate high voltage and the OFF level is equivalent to 10% of the gate high voltage.

Assignees

Inventors

Classifications

  • Improving the luminance or brightness uniformity across the screen · CPC title

  • G09G3/3233Primary

    with pixel circuitry controlling the current through the light-emitting element · CPC title

  • in which the data driver supplies a variable data voltage for setting the current through, or the voltage across, the light-emitting elements · CPC title

  • G09G3/32Primary

    semiconductive, e.g. using light-emitting diodes [LED] · CPC title

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What does patent US9626906B2 cover?
Disclosed is an organic light emitting display in which a sensing period during which the source voltage of the driving TFT is raised toward a data voltage applied to a gate electrode of the driving TFT in order to compensate a change in mobility of the driving TFT, a first gate signal is maintained at an ON level and a second gate signal is maintained at an OFF level, and the first and second …
Who is the assignee on this patent?
Lg Display Co Ltd
What technology area does this patent fall under?
Primary CPC classification G09G3/3233. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Apr 18 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).